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公开(公告)号：US11915008B2
公开(公告)日：2024-02-27
申请号：US17654537
申请日：2022-03-11
IPC分类号： G06F9/44 , G06F9/4401 , G06F9/30
CPC分类号： G06F9/4403 , G06F9/30101
摘要： In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.
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2.发明授权公开(公告)号：US11321492B2
公开(公告)日：2022-05-03
申请号：US17107183
申请日：2020-11-30
IPC分类号： G06F9/448 , G06F12/02 , G06F9/38 , G06F9/30 , G06F21/71 , G06F21/60 , H04L9/06 , G06F11/07 , G06F21/57 , G06F21/72 , G06F21/77 , H03K19/17728
摘要： A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.
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公开(公告)号：US11921910B2
公开(公告)日：2024-03-05
申请号：US17443497
申请日：2021-07-27
IPC分类号： G06F21/83 , G06F9/38 , G06F9/445 , G06F12/02 , G06F21/57 , G06F21/64 , G06F21/74 , G09C1/00 , H04L9/32 , H04L9/40 , H04W4/40 , H04W12/03 , H04W12/106 , H04W12/40
CPC分类号： G06F21/83 , G06F9/3816 , G06F9/445 , G06F12/02 , G06F21/57 , G06F21/64 , G06F21/74 , G09C1/00 , H04L9/3234 , H04W12/106 , G06F2212/7209 , H04L63/0853 , H04W4/40 , H04W12/03 , H04W12/40
摘要： A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.
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4.发明申请公开(公告)号：US20190007202A1
公开(公告)日：2019-01-03
申请号：US16022110
申请日：2018-06-28
摘要： A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.
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5.发明申请公开(公告)号：US20180330127A1
公开(公告)日：2018-11-15
申请号：US15975460
申请日：2018-05-09
CPC分类号： G06F21/83 , G06F9/3816 , G06F9/445 , G06F12/02 , G06F21/57 , G06F21/64 , G06F21/74 , G06F2212/7209 , H04L9/3234 , H04L63/0853
摘要： A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.
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公开(公告)号：US11977424B2
公开(公告)日：2024-05-07
申请号：US17702529
申请日：2022-03-23
IPC分类号： G06F1/24
CPC分类号： G06F1/24
摘要： A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down. During the software runtime phase, the first circuitry activate a weak pull-down for implementing a bidirectional reset terminal or activates a weak pull-up resistance for implementing a reset output terminal, and the second circuitry activates a weak pull-up for implementing a reset input terminal or activates a strong pull-up for implementing a reset output terminal.
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公开(公告)号：US11032067B2
公开(公告)日：2021-06-08
申请号：US16022110
申请日：2018-06-28
摘要： A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.
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公开(公告)号：US20200341836A1
公开(公告)日：2020-10-29
申请号：US16928768
申请日：2020-07-14
摘要： In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
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公开(公告)号：US20190007201A1
公开(公告)日：2019-01-03
申请号：US16022033
申请日：2018-06-28
摘要： A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.
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公开(公告)号：US20230170006A1
公开(公告)日：2023-06-01
申请号：US18056803
申请日：2022-11-18
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N. V. , STMicroelectronics Application GMBH
CPC分类号： G11C7/24 , G11C7/1039 , G11C7/1069
摘要： In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.
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