公开(公告)号：US20060101208A1

公开(公告)日：2006-05-11

申请号：US10985484

申请日：2004-11-09

Applicant: Sailesh Kottapalli

Inventor： Sailesh Kottapalli

IPC: G06F12/00

CPC classification number: G06F12/127

Abstract: A method and apparatus for supporting temporal data and non-temporal data memory accesses in a cache is disclosed. In one embodiment, a specially selected way in a set is generally used for non-temporal data memory accesses. A non-temporal flag may be associated with this selected way. In one embodiment, cache lines from memory accesses including a non-temporal hint may be generally placed into the selected way, and the non-temporal flag then set. When a temporal data cache line is to be loaded into a set, it may overrule the normal replacement method when the non-temporal flag is set, and be loaded into that selected way.

Abstract translation: 公开了一种用于支持高速缓存中的时间数据和非时间数据存储器访问的方法和装置。 在一个实施例中，集合中特别选择的方式通常用于非时间数据存储器访问。 非时间标志可以与该选择的方式相关联。 在一个实施例中，包括非时间提示的存储器访问的高速缓存行通常可以被放置成所选择的方式，然后设置非时间标志。 当时间数据高速缓存行被加载到集合中时，当设置非时间标志时，它可能会推翻正常的替换方法，并将其加载到所选择的方式中。

公开(公告)号：US20050138332A1

公开(公告)日：2005-06-23

申请号：US10739686

申请日：2003-12-17

Applicant: Sailesh Kottapalli ,  Richard Goe ,  Youngsoo Choi

Inventor： Sailesh Kottapalli ,  Richard Goe ,  Youngsoo Choi

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3861

Abstract: A method and apparatus for using result-speculative data under run-ahead speculative execution is disclosed. In one embodiment, the uncommitted target data from instructions being run-ahead executed may be saved into an advance data table. This advance data table may be indexed by the lines in the instruction buffer containing the instructions for run-ahead execution. When the instructions are re-executed subsequent to the run-ahead execution, valid target data may be retrieved from the advance data table and supplied as part of a zero-clock bypass to support parallel re-execution. This may achieve parallel execution of dependent instructions. In other embodiments, the advance data table may be content-addressable-memory searchable on target registers and supply target data to general speculative execution.

Abstract translation: 公开了一种在预先推测执行下使用结果推测数据的方法和装置。 在一个实施例中，来自正在执行的预定指令的未提交的目标数据可以被保存到提前数据表中。 该提前数据表可以由包含用于预先执行的指令的指令缓冲器中的行进行索引。 当在超前执行之后重新执行指令时，可以从提前数据表中检索有效的目标数据，并作为零时钟旁路的一部分提供以支持并行重新执行。 这可以实现依赖指令的并行执行。 在其他实施例中，提前数据表可以是内容寻址存储器，可在目标寄存器上搜索，并将目标数据提供给一般推测执行。

公开(公告)号：US20050050296A1

公开(公告)日：2005-03-03

申请号：US10650335

申请日：2003-08-28

Applicant: Sailesh Kottapalli ,  Nadeem Firasta

Inventor： Sailesh Kottapalli ,  Nadeem Firasta

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1054 ,  G06F12/1036

Abstract: A method and system for allowing a multi-threaded processor to share pages across different threads in a pre-validated cache using a translation look-aside buffer is disclosed. The multi-threaded processor searches a translation look-aside buffer in an attempt to match a virtual memory address. If no matching valid virtual memory address is found, a new translation is retrieved and the translation look-aside buffer is searched for a matching physical memory address. If a matching physical memory address is found, the old translation is overwritten with a new translation. The multi-threaded processor may execute switch on event multi-threading or simultaneous multi-threading. If simultaneous multi-threading is executed, then access rights for each thread is associated with the translation.

Abstract translation: 公开了一种允许多线程处理器使用翻译后备缓冲器在预先验证的高速缓存中的不同线程上共享页面的方法和系统。 多线程处理器搜索翻译后备缓冲区以尝试匹配虚拟内存地址。 如果没有找到匹配的有效虚拟内存地址，则检索新的翻译，并搜索匹配的物理内存地址的翻译后备缓冲区。 如果找到匹配的物理内存地址，则使用新的翻译覆盖旧的翻译。 多线程处理器可以执行切换事件多线程或同时多线程。 如果同时执行多线程，则每个线程的访问权限与翻译相关联。

公开(公告)号：US10204049B2

公开(公告)日：2019-02-12

申请号：US13808595

申请日：2012-01-06

Applicant: Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Sailesh Kottapalli ,  Ganesh Kumar ,  Henk G. Neefs ,  Neil J. Achtman ,  Bongjin Jung

Inventor： Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Sailesh Kottapalli ,  Ganesh Kumar ,  Henk G. Neefs ,  Neil J. Achtman ,  Bongjin Jung

IPC: G06F12/084 ,  G06F12/0817

Abstract: Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.

公开(公告)号：US20140281270A1

公开(公告)日：2014-09-18

申请号：US13835862

申请日：2013-03-15

Applicant: Henk G. Neefs ,  Ganesh Kumar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Sailesh Kottapalli ,  Jeffrey S. Wilder

Inventor： Henk G. Neefs ,  Ganesh Kumar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Sailesh Kottapalli ,  Jeffrey S. Wilder

IPC: G06F12/08

CPC classification number: G06F12/0813 ,  G06F12/0817 ,  G06F12/082

Abstract: Methods and apparatus relating to directory based coherency to improve input/output write bandwidth in scalable systems are described. In one embodiment, a first agent receives a request to write data from a second agent via a link and logic causes the first agent to write the directory state to an Input/Output Directory Cache (IODC) of the first agent. Additionally, the logic causes the second agent to send data from a modified state to an exclusive state using write back to the first agent, while allowing the data to remain cached exclusively in the second agent and also enabling the deallocation of the IODC entry in the first agent. Other embodiments are also disclosed.

Abstract translation: 描述了与基于目录的一致性相关的方法和装置，以改善可扩展系统中的输入/输出写入带宽。 在一个实施例中，第一代理接收经由链路从第二代理程序写入数据的请求，并且逻辑使得第一代理将目录状态写入第一代理的输入/输出目录高速缓存（IODC）。 此外，逻辑使得第二代理使用回写到第一代理将数据从修改状态发送到独占状态，同时允许数据保持高速缓存在第二代理中，并且还允许在I / 第一代理 还公开了其他实施例。

公开(公告)号：US08301907B2

公开(公告)日：2012-10-30

申请号：US11863563

申请日：2007-09-28

Applicant: Mahesh S. Natu ,  Sham Datta ,  Jeff Wiedemeier ,  James R. Vash ,  Sailesh Kottapalli ,  Scott P. Bobholz ,  Allen Baum

Inventor： Mahesh S. Natu ,  Sham Datta ,  Jeff Wiedemeier ,  James R. Vash ,  Sailesh Kottapalli ,  Scott P. Bobholz ,  Allen Baum

IPC: G06F11/30

CPC classification number: G06F15/16

Abstract: Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.

Abstract translation: 提供了在LaGrande Technology（LT）控制下启动可靠性，可用性和可维护性特性后，提供可靠性，可用性和可维护性功能的系统和方法，或者可比较的安全技术，而不会影响安全性。 在一个实施例中，该方法包括将至少一个特定能力添加到处理器，以实现CPU热插拔，CPU迁移，CPU热去除和按需容量中的至少一个。

公开(公告)号：US08205204B2

公开(公告)日：2012-06-19

申请号：US12359113

申请日：2009-01-23

Applicant: Ken Shoemaker ,  Sailesh Kottapalli ,  Kin-Kee Sit

Inventor： Ken Shoemaker ,  Sailesh Kottapalli ,  Kin-Kee Sit

IPC: G06F9/46 ,  G06F15/00

CPC classification number: G06F9/3802 ,  G06F9/3851 ,  G06F9/3885

Abstract: An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread. A multi-thread scheduler coupled to the instruction fetch units and a execution unit. The multi-thread scheduler determines the width of the execution unit and the execution unit executes the threads accordingly.

Abstract translation: 提供多线程处理器。 多线程处理器包括接收第一线程的第一指令获取单元和用于接收第二线程的第二指令获取单元。 耦合到指令提取单元和执行单元的多线程调度器。 多线程调度器确定执行单元的宽度，并且执行单元相应地执行线程。

公开(公告)号：US20120144089A1

公开(公告)日：2012-06-07

申请号：US13250223

申请日：2011-09-30

Applicant: Jonathan C. Hall ,  Sailesh Kottapalli ,  Andrew T. Forsyth

Inventor： Jonathan C. Hall ,  Sailesh Kottapalli ,  Andrew T. Forsyth

IPC: G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/345 ,  G06F12/06 ,  G06F12/08

Abstract: Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.

Abstract translation: 公开了用于访问用于散射/收集操作的多条数据高速缓存行的方法和装置。 设备的实施例可以包括地址生成逻辑，用于从具有第一值的一组对应的掩码元素中的每一个的索引集合的索引生成地址。 线或库匹配排序逻辑匹配相同高速缓存行或不同库中的地址，并且订购访问序列以允许多个高速缓存行和不同存储体中的一组地址。 地址选择逻辑将地址组指向高速缓存中的对应的不同存储体，以访问与单个访问周期中的地址组对应的多个高速缓存行中的数据元素。 拆卸/重组缓冲器根据其各自的存储体/寄存器位置对数据元素进行排序，并且收集/散布有限状态机将相应的掩模元素的值从第一值改变为第二值。

公开(公告)号：US07937709B2

公开(公告)日：2011-05-03

申请号：US11026207

申请日：2004-12-29

Applicant: Sailesh Kottapalli ,  John H. Crawford

Inventor： Sailesh Kottapalli ,  John H. Crawford

IPC: G06F9/46 ,  G06F9/44

CPC classification number: G06F9/522 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0857

Abstract: In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括为多个线程中的每个线程分配共享变量内的位置并将值写入相应位置以指示相应线程已经达到屏障的方法。 以这种方式，当所有线程都到达障碍物时，建立同步。 在一些实施例中，共享变量可以存储在可由多个线程访问的高速缓存中。 描述和要求保护其他实施例。

公开(公告)号：US20110055493A1

公开(公告)日：2011-03-03

申请号：US12943314

申请日：2010-11-10

Applicant: Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

Inventor： Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

IPC: G06F12/14

CPC classification number: G06F9/528 ,  G06F9/3834 ,  G06F9/544

Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

Abstract translation: 本文描述的装置和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。 在软件中划分的事务被推测执行。 在执行期间，无效远程访问/请求到从共享存储器加载并被写入到共享存储器的地址由事务缓冲器跟踪。 如果遇到无效访问，则重新执行该事务。 在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。