公开(公告)号：US11581297B2

公开(公告)日：2023-02-14

申请号：US17026637

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Bongsoon Lim ,  Hongsoo Jeon ,  Jaeduk Yu

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  G11C16/08 ,  G11C16/04

Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

公开(公告)号：US10381078B2

公开(公告)日：2019-08-13

申请号：US15992840

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Dong-Kil Yun ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C14/00 ,  H01L27/11578 ,  H01L27/108 ,  H01L27/1157 ,  G11C11/4094 ,  G11C11/408 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/4091 ,  G11C16/04

Abstract: A semiconductor memory includes a first memory cell array in a first region of a substrate and a second memory cell array in a second region of the substrate. The first memory cell array includes cell strings, and each cell string includes non-volatile memory cells stacked in a direction perpendicular to the substrate. The second memory cell array includes volatile memory cells, and each volatile memory cell includes a select transistor and a capacitor. The capacitor includes at least one contact electrically connected with the select transistor and having a second height corresponding to a first height of each cell string, and at least one second contact supplied with a ground voltage, having a third height corresponding to the first height of each cell string, adjacent to the at least one first contact, and electrically disconnected with the at least one first contact.