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公开(公告)号:US10381078B2
公开(公告)日:2019-08-13
申请号:US15992840
申请日:2018-05-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chanho Kim , Dong-Kil Yun , Pansuk Kwak , Hongsoo Jeon
IPC: G11C14/00 , H01L27/11578 , H01L27/108 , H01L27/1157 , G11C11/4094 , G11C11/408 , G11C16/08 , G11C16/10 , G11C16/26 , G11C11/4091 , G11C16/04
Abstract: A semiconductor memory includes a first memory cell array in a first region of a substrate and a second memory cell array in a second region of the substrate. The first memory cell array includes cell strings, and each cell string includes non-volatile memory cells stacked in a direction perpendicular to the substrate. The second memory cell array includes volatile memory cells, and each volatile memory cell includes a select transistor and a capacitor. The capacitor includes at least one contact electrically connected with the select transistor and having a second height corresponding to a first height of each cell string, and at least one second contact supplied with a ground voltage, having a third height corresponding to the first height of each cell string, adjacent to the at least one first contact, and electrically disconnected with the at least one first contact.
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公开(公告)号:US20190130974A1
公开(公告)日:2019-05-02
申请号:US15992840
申请日:2018-05-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chanho Kim , Dong-Kil Yun , Pansuk Kwak , Hongsoo Jeon
IPC: G11C14/00 , H01L27/11578 , H01L27/108 , H01L27/1157
CPC classification number: G11C14/0018 , G11C11/005 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , H01L27/10808 , H01L27/10847 , H01L27/1157 , H01L27/11578
Abstract: A semiconductor memory includes a first memory cell array in a first region of a substrate and a second memory cell array in a second region of the substrate. The first memory cell array includes cell strings, and each cell string includes non-volatile memory cells stacked in a direction perpendicular to the substrate. The second memory cell array includes volatile memory cells, and each volatile memory cell includes a select transistor and a capacitor. The capacitor includes at least one contact electrically connected with the select transistor and having a second height corresponding to a first height of each cell string, and at least one second contact supplied with a ground voltage, having a third height corresponding to the first height of each cell string, adjacent to the at least one first contact, and electrically disconnected with the at least one first contact.
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公开(公告)号:US10394115B2
公开(公告)日:2019-08-27
申请号:US15442780
申请日:2017-02-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Kil Yun , Sunghoon Kim , Jae-Eun Lee , Hyangja Yang
Abstract: A method for verifying mask data in a computing device includes receiving layout data, receiving mask data, determining an interaction number between a pattern corresponding to the layout data and a pattern corresponding to the mask data, and detecting an error of the mask data based on the interaction number.
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