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公开(公告)号：US12107061B2
公开(公告)日：2024-10-01
申请号：US17513132
申请日：2021-10-28
发明人： Homoon Shin , Jooyong Park , Hongsoo Jeon , Pansuk Kwak
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H01L25/18
CPC分类号： H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： An integrated circuit device includes; a peripheral circuit structure including a peripheral circuit, a first insulating layer covering the peripheral circuit, extension lines in the first insulating layer, and a first bonding pad in the first insulating layer, and a cell array structure including a conductive plate, a memory cell array below the conductive plate, a second insulating layer covering the memory cell array, a second bonding pad in the second insulating layer, a conductive via on the conductive plate, and a line connected to the conductive via. The first bonding pad contacts the second bonding pad, and the integrated circuit device further includes contact plugs electrically connecting the line to the extension lines.
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公开(公告)号：US20240071517A1
公开(公告)日：2024-02-29
申请号：US18504093
申请日：2023-11-07
发明人： Seungyeon Kim , Daeseok Byeon , Pansuk Kwak , Hongsoo Jeon
摘要： A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.
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公开(公告)号：US11837293B2
公开(公告)日：2023-12-05
申请号：US17898885
申请日：2022-08-30
发明人： Seungyeon Kim , Daeseok Byeon , Pansuk Kwak , Hongsoo Jeon
摘要： A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.
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公开(公告)号：US11355194B2
公开(公告)日：2022-06-07
申请号：US16942299
申请日：2020-07-29
发明人： Kyunghwa Yun , Chanho Kim , Pansuk Kwak
IPC分类号： G11C16/08 , G11C16/10 , H01L27/11582 , H01L27/1157 , H01L27/11573
摘要： A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.
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公开(公告)号：US11211391B2
公开(公告)日：2021-12-28
申请号：US16814491
申请日：2020-03-10
发明人： Kyunghwa Yun , Pansuk Kwak , Chanho Kim , Dongku Kang
IPC分类号： G11C16/04 , H01L27/11556 , H01L27/11582 , G11C5/06 , G11C5/02
摘要： A memory device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder; a cell array region including wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating through the wordlines; and a cell contact region including cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction. Each of the first and second cell contact regions includes first pads having different lengths to each other in the first direction and second pads different from the first pads, and the cell contacts are connected to the wordlines in the first pads. The number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region.
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公开(公告)号：US11901033B2
公开(公告)日：2024-02-13
申请号：US18149302
申请日：2023-01-03
发明人： Jooyong Park , Minsu Kim , Daeseok Byeon , Pansuk Kwak
IPC分类号： G11C29/00 , G06F11/20 , G11C16/04 , G11C29/44 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/12 , G11C29/02 , G11C29/52 , G11C29/42 , G11C29/24
CPC分类号： G11C29/838 , G06F11/2094 , G11C16/0483 , G11C29/44 , G11C16/10 , G11C16/26 , G11C16/349 , G11C16/3472 , G11C29/02 , G11C29/24 , G11C29/42 , G11C29/4401 , G11C29/52 , G11C29/70 , G11C29/702 , G11C29/785 , G11C29/789 , G11C2029/1204
摘要： A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.
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公开(公告)号：US11895842B2
公开(公告)日：2024-02-06
申请号：US17345832
申请日：2021-06-11
发明人： Changyeon Yu , Pansuk Kwak
IPC分类号： G11C16/04 , H10B43/40 , H01L21/66 , H01L23/535 , H10B41/27 , H10B41/41 , H10B43/27 , G11C16/24
CPC分类号： H10B43/40 , H01L22/34 , H01L23/535 , H10B41/27 , H10B41/41 , H10B43/27 , G11C16/0483 , G11C16/24
摘要： A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent to the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.
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公开(公告)号：US11189634B2
公开(公告)日：2021-11-30
申请号：US16705395
申请日：2019-12-06
发明人： Kyunghwa Yun , Chanho Kim , Pansuk Kwak
IPC分类号： H01L27/11582 , H01L23/528 , H01L27/11573 , H01L29/78 , H01L29/10 , G11C16/04 , G11C16/14 , G11C16/26 , G11C16/10 , G11C16/08 , H01L27/11565 , H01L23/532
摘要： A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.
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公开(公告)号：US09589643B2
公开(公告)日：2017-03-07
申请号：US15226941
申请日：2016-08-03
发明人： Chul-Jin Hwang , Pansuk Kwak , Younghwan Ryu
IPC分类号： G11C16/04 , G11C16/08 , H01L27/115
CPC分类号： G11C16/08 , G11C5/025 , G11C8/10 , G11C8/12 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.
摘要翻译： 非易失性存储器件包括存储单元阵列，其包括在与衬底正交的方向上堆叠的单元串，并且包括分隔单元串的第一子串组和第二子串组以及经由单元串连接到单元串的存储单元的地址解码器 多个字线并且被配置为向存储器单元提供工作电压，其中地址解码器设置在第一子串组和第二子串组之间。
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公开(公告)号：US09424928B2
公开(公告)日：2016-08-23
申请号：US14817281
申请日：2015-08-04
发明人： Chul-Jin Hwang , Pansuk Kwak , Younghwan Ryu
CPC分类号： G11C16/08 , G11C5/025 , G11C8/10 , G11C8/12 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.
摘要翻译： 非易失性存储器件包括存储单元阵列，其包括在与衬底正交的方向上堆叠的单元串，并且包括分隔单元串的第一子串组和第二子串组以及经由单元串连接到单元串的存储单元的地址解码器 多个字线并且被配置为向存储器单元提供工作电压，其中地址解码器设置在第一子串组和第二子串组之间。
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