公开(公告)号：US20180190829A1

公开(公告)日：2018-07-05

申请号：US15647903

申请日：2017-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min SONG ,  Woo Seok PARK ,  Geum Jong BAE ,  Dong Il BAE ,  Jung Gil YANG

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.

公开(公告)号：US20180158908A1

公开(公告)日：2018-06-07

申请号：US15877667

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil YANG ,  Dong II BAE ,  Chang Woo SOHN ,  Seung Min SONG ,  Dong Hun LEE

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8238

CPC classification number: H01L29/0673 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.