公开(公告)号：US20200373402A1

公开(公告)日：2020-11-26

申请号：US16732520

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil YANG ,  Seung Min SONG ,  Soo Jin JEONG ,  Dong Il BAE ,  Bong Seok SUH

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

公开(公告)号：US20180090569A1

公开(公告)日：2018-03-29

申请号：US15463551

申请日：2017-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil YANG ,  Dong ll BAE ,  Chang Woo SOHN ,  Seung Min SONG ,  Dong Hun LEE

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L27/02 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

公开(公告)号：US20230389257A1

公开(公告)日：2023-11-30

申请号：US18076963

申请日：2022-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min SONG ,  Hyo-Jin KIM ,  Kyung Hee CHO

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: A semiconductor device includes a substrate, a lower active pattern which is spaced apart from the substrate and extends in a first direction, an upper active pattern on the lower active pattern, the upper active pattern being spaced apart from the lower active pattern and extending in the first direction, a gate structure on the substrate, the gate structure extending in a second direction intersecting the first direction, and a cutting pattern on the substrate, the cutting pattern extending in the first direction to cut the gate structure. The gate structure includes a lower gate electrode through which the lower active pattern penetrates, an upper gate electrode which is connected to the lower gate electrode and through which the upper active pattern penetrates, and an insulating pattern on one side of the cutting pattern, the insulating pattern being arranged with the upper gate electrode along the second direction.

公开(公告)号：US20230352523A1

公开(公告)日：2023-11-02

申请号：US18079537

申请日：2022-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Min SONG ,  Myung Il KANG ,  Do Young CHOI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0649 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, an active pattern on the substrate, a plurality of lower nanosheets stacked on the active pattern, a separation structure spaced apart from the plurality of lower nanosheets in the vertical direction and disposed on the plurality of lower nanosheets, and including first to third layers sequentially stacked on each other, a plurality of upper nanosheets spaced apart from the separation structure in the vertical direction and disposed on the separation structure, and stacked on the separation structure, and a gate electrode extending in a second horizontal direction different from the first horizontal direction, and surrounding the separation structure, each of the plurality of lower nanosheets, and each of the plurality of upper nanosheets. The first and third layers include the same material, and each of the first layer and the third layer includes a material different from a material of the second layer.

公开(公告)号：US20220310852A1

公开(公告)日：2022-09-29

申请号：US17840737

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Woo Seok PARK ,  Dong Chan SUH ,  Seung Min SONG ,  Geum Jong BAE ,  Dong Il BAE

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

公开(公告)号：US20210111186A1

公开(公告)日：2021-04-15

申请号：US16852907

申请日：2020-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Min KIM ,  Seung Min SONG ,  Jae Hoon SHIN ,  Joong Shik SHIN ,  Geun Won LIM

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/311

Abstract: A nonvolatile memory device with improved product reliability and a method of fabricating the same is provided. The nonvolatile memory device comprises a substrate, a first mold structure disposed on the substrate and including a plurality of first gate electrodes, a second mold structure disposed on the first mold structure and including a plurality of second gate electrodes and a plurality of channel structures intersecting the first gate electrodes and the second gate electrodes by penetrating the first and second mold structures, wherein the first mold structure includes first and second stacks, which are spaced apart from each other, and the second mold structure includes a third stack, which is stacked on the first stack, a fourth stack, which is stacked on the second stack, and first connecting parts, which connect the third and fourth stacks.

公开(公告)号：US20190296107A1

公开(公告)日：2019-09-26

申请号：US16423641

申请日：2019-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil YANG ,  Dong II BAE ,  Chang Woo SOHN ,  Seung Min SONG ,  Dong Hun LEE

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/08 ,  H01L29/786

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

公开(公告)号：US20190088789A1

公开(公告)日：2019-03-21

申请号：US16161765

申请日：2018-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min SONG ,  Woo Seok PARK ,  Geum Jong BAE ,  Dong Il BAE ,  Jung Gil YANG

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423

Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.

公开(公告)号：US20170256608A1

公开(公告)日：2017-09-07

申请号：US15444550

申请日：2017-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Dae SUK ,  Seung Min SONG ,  Geum Jong BAE

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/786

Abstract: A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate. The spacer connector may connect the first gate spacer and the second gate spacer to each other.

公开(公告)号：US20240290853A1

公开(公告)日：2024-08-29

申请号：US18373058

申请日：2023-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min SONG ,  Panjae PARK ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L29/40

CPC classification number: H01L29/41766 ,  H01L29/401

Abstract: Provided is a semiconductor device which includes: a backside contact plug, formed at a back side of the semiconductor device, below a source/drain region connected to the backside contact plug, wherein the backside contact plug includes a 1st portion which is not vertically overlapped by the circuit element.