公开(公告)号：US10733119B2

公开(公告)日：2020-08-04

申请号：US16165139

申请日：2018-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changho Yun ,  Sung-Joon Kim

IPC: G11C7/00 ,  G06F13/16 ,  G11C11/406 ,  G11C7/10 ,  G11C29/00 ,  G11C5/04

Abstract: A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.

公开(公告)号：US20200034666A1

公开(公告)日：2020-01-30

申请号：US16268762

申请日：2019-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Jin Yun ,  Sung-Joon Kim ,  Sang-Hoan Chang

IPC: G06K9/62 ,  G06K9/00

Abstract: An object recognition device including an artificial neural network (NN) engine configured to receive learning data and weights, make an object recognition model (ORM) learn by using the received information, and provide selected weight data including weights from the selected portion of the weights, and further configured to receive a feature vector, and apply the feature vector extracted from an object data that constructs the object and the selected weight data to the learned ORM to provide an object recognition result, a nonvolatile memory (NVM) configured to store the learned ORM, and an error correction code (ECC) engine configured to perform an ECC encoding on the selected weight data to generate parity data, provide the selected weight data and the parity data to the NVM, and provide the selected weight data to the NN engine by performing an ECC decoding on the selected weight data based on the parity data.

公开(公告)号：US20190310784A1

公开(公告)日：2019-10-10

申请号：US16205357

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Joon Kim ,  Dae-Jeong Kim ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

IPC: G06F3/06

Abstract: A memory module includes a first type memory, a second type memory, a serial presence detect device and a controller. The serial presence detect device is configured to transfer capacity information of the second type memory to an external host device, during an initialization operation. The controller is configured to transfer a training command for the second type memory received from the external host device to the first type memory, during a training operation, which follows in time the initialization operation.

公开(公告)号：US20190310783A1

公开(公告)日：2019-10-10

申请号：US16363034

申请日：2019-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US10108563B2

公开(公告)日：2018-10-23

申请号：US15659182

申请日：2017-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changho Yun ,  Sung-Joon Kim

IPC: G11C7/00 ,  G06F13/16 ,  G11C11/406

Abstract: A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.

公开(公告)号：US08982620B2

公开(公告)日：2015-03-17

申请号：US14044892

申请日：2013-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Kil Lee ,  Sung-Joon Kim ,  Jin-Yub Lee ,  Sung-Kyu Jo ,  Seung-Jae Lee ,  Jong-Hoon Lee

IPC: G11C16/04 ,  G11C16/22

CPC classification number: G11C16/22 ,  G06F12/0246

Abstract: A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block.

Abstract translation: 一种操作非易失性存储器的方法包括： 在上电期间，从信息块读取控制信息并从附加信息块中锁定信息，然后在确定应该锁定安全块时，产生禁止访问存储在安全块中的数据的锁定使能信号，以及 只读使能信号，防止存储在附加信息块中的数据发生变化。