公开(公告)号：US12158809B2

公开(公告)日：2024-12-03

申请号：US18295457

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Young Lee ,  Sung-Joon Kim ,  Ilho Kim ,  Kyungjin Park ,  Changho Yun ,  Jinhun Jeong ,  Insu Choi ,  Kyung-Hee Han ,  Yukyoung Kim ,  Jinwoo Kim ,  Chaeeun Lee ,  Yunmi Hwang

IPC: G06F11/10 ,  G06F11/07

Abstract: Disclosed is an electronic device including a memory module that includes at least one dynamic random access memory, and a processor configured to access the memory module, determine a corrected error count associated with an address of a corrected error in response to the corrected error being detected when data are read from the memory module, read an error log associated with the corrected error, determine a risk level of the corrected error based on the error log, and schedule a post package repair (PPR) for the address of the corrected error in response to the risk level of the corrected error being high.

公开(公告)号：US20240168846A1

公开(公告)日：2024-05-23

申请号：US18328959

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinhun JEONG ,  Sung-Joon Kim ,  Ilho Kim ,  Kyungjin Park ,  Changho Yun ,  Ho-Young Lee ,  Jongwon Jeong ,  Insu Choi ,  Kyung-Hee Han ,  Yunmi Hwang

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/14

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1438

Abstract: A method for preparing error recovery of a memory device included in a memory system includes performing a training operation of the memory device upon power-on of the memory system, booting an operating system into a normal mode by operating the memory device using a selected operation frequency of a plurality of operation frequencies based on results of the training operation, detecting an error frequency among the plurality of operation frequencies in response to a change of the selected operation frequency of the memory device by the operating system, the error frequency being an operation frequency which causes at least one error in the memory device, and storing information regarding the detected error frequency in a first register included in a memory controller associated with the memory device.

公开(公告)号：US20200174882A1

公开(公告)日：2020-06-04

申请号：US16412468

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/00 ,  G11C11/406

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

公开(公告)号：US11474717B2

公开(公告)日：2022-10-18

申请号：US17082448

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US10852969B2

公开(公告)日：2020-12-01

申请号：US16363034

申请日：2019-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US10790026B2

公开(公告)日：2020-09-29

申请号：US16174839

申请日：2018-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il-Su Han ,  Sung-Joon Kim ,  Jong-Hwa Kim ,  Da-Hee Jeong

IPC: G11C16/10 ,  G11C16/08 ,  G11C7/10 ,  G06F12/00 ,  G06F13/00

Abstract: A non-volatile memory device includes a non-volatile memory cell array, an input/output pad unit, and a peripheral circuit. The non-volatile memory device executes an operation requested by a controller. The input/output pad component provides a path through which a command and data related to the operation requested by the controller are input to the non-volatile memory device, and through which a result of execution of the requested operation is output to the controller. The peripheral circuit is configured to be loaded with a plurality of commands provided by the controller, to temporarily store program data provided by the controller to be written in the non-volatile memory cell array and data read from the non-volatile memory cell array, to adjust an execution order of the commands asynchronously with the controller based on an internal operation status of the non-volatile memory device, and to execute the commands in the adjusted execution order.

公开(公告)号：US10325643B2

公开(公告)日：2019-06-18

申请号：US15691828

申请日：2017-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Ho Yun ,  Min-Su Kim ,  Sung-Joon Kim ,  So-Ra Park ,  Hyun-Jung Yoo

IPC: G06F3/06 ,  G11C11/406

Abstract: A method of operating a memory device, a first setting signal is received by a first memory device among a plurality of memory devices. The first memory device has a first storage capacity, and the memory devices may be connected to one another by a single channel. A second setting signal is received by a second memory device among the plurality of memory devices. The second memory device has a second storage capacity different from the first storage capacity. N refresh operations are performed by the first memory device based on a first refresh command and the first setting signal during a first refresh period. M refresh operations are performed by the second memory device based on a second refresh command and the second setting signal during a second refresh period. A duration of the second refresh period is substantially the same as a duration of the first refresh period.

公开(公告)号：US20230196753A1

公开(公告)日：2023-06-22

申请号：US18171579

申请日：2023-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Jin YUN ,  Sung-Joon Kim ,  Sang-Hoan Chang

IPC: G06V10/82 ,  G06V20/00 ,  G06F18/21 ,  G06F18/214 ,  G06V30/19 ,  G06V30/226

CPC classification number: G06V10/82 ,  G06V20/00 ,  G06F18/217 ,  G06F18/214 ,  G06V30/19173 ,  G06V30/2272

Abstract: An object recognition device including an artificial neural network (NN) engine configured to receive learning data and weights, make an object recognition model (ORM) learn by using the received information, and provide selected weight data including weights from the selected portion of the weights, and further configured to receive a feature vector, and apply the feature vector extracted from an object data that constructs the object and the selected weight data to the learned ORM to provide an object recognition result, a nonvolatile memory (NVM) configured to store the learned ORM, and an error correction code (ECC) engine configured to perform an ECC encoding on the selected weight data to generate parity data, provide the selected weight data and the parity data to the NVM, and provide the selected weight data to the NN engine by performing an ECC decoding on the selected weight data based on the parity data.

公开(公告)号：US11210208B2

公开(公告)日：2021-12-28

申请号：US16162821

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Jiseok Kang ,  Tae-Kyeong Ko ,  Sung-Joon Kim ,  Wooseop Kim ,  Chanik Park ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

IPC: G06F12/02 ,  G11C11/56 ,  G06F3/06 ,  G06F13/16

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

公开(公告)号：US10922170B2

公开(公告)日：2021-02-16

申请号：US16412468

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/406 ,  G11C11/00 ,  G11C29/52

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.