公开(公告)号：US20110222010A1

公开(公告)日：2011-09-15

申请号：US13043034

申请日：2011-03-08

Applicant: Jae-Young Lee ,  Ju-Yeon Seo ,  Seong-Jun Lee ,  Yi Li ,  Seong-Ryong Lee ,  Yong-Kyu Jang

Inventor： Jae-Young Lee ,  Ju-Yeon Seo ,  Seong-Jun Lee ,  Yi Li ,  Seong-Ryong Lee ,  Yong-Kyu Jang

IPC: G02F1/1343 ,  H01J9/20

CPC classification number: G02F1/134336 ,  G02F1/133788 ,  G02F2001/133726 ,  G02F2001/133776

Abstract: A display device having an improved viewing angle by using a linear polarization structure, and a method of manufacturing the same. The display device includes a first substrate arrangement including a domain forming layer and a pixel electrode arranged on the domain forming layer, the pixel electrode having a cross type opening pattern, a second substrate arrangement including a common electrode arranged on an entire surface that faces the first substrate arrangement and a liquid crystal layer arranged between the first substrate arrangement and the second substrate arrangement, the liquid crystal layer including a plurality of liquid crystal molecules and a reactive mesogen to fix liquid crystal molecules and to produce a liquid crystal domain based on the cross type opening pattern.

Abstract translation: 通过使用线偏振结构具有改善的视角的显示装置及其制造方法。 显示装置包括：第一基板装置，其包括域形成层和布置在畴形成层上的像素电极，像素电极具有交叉型开口图案;第二基板布置，包括布置在面向 第一衬底布置和布置在第一衬底布置和第二衬底布置之间的液晶层，液晶层包括多个液晶分子和反应性液晶原子，用于固定液晶分子并基于该液晶分子产生液晶畴 十字型开口图案。

公开(公告)号：US07956659B2

公开(公告)日：2011-06-07

申请号：US11647645

申请日：2006-12-29

Applicant: Min-Young You ,  Seong-Jun Lee

Inventor： Min-Young You ,  Seong-Jun Lee

IPC: H03L7/00

CPC classification number: H03L7/0812 ,  G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  H03K5/1565

Abstract: A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.

Abstract translation: 半导体存储器件包括：第一时钟缓冲器，用于响应于系统时钟信号的反相信号输出第一内部时钟信号，并用于响应于控制信号来校正第一内部时钟信号的占空比; 第二时钟缓冲器，用于响应于所述系统时钟信号输出第二内部时钟信号，并用于响应于所述控制信号来校正所述第二内部时钟信号的占空比; 模拟占空比校正电路，用于输出对应于第一和第二内部时钟信号的占空比的控制信号; 混合电路，用于混合第一和第二内部时钟信号，并输出其占空比被校正的第三内部时钟信号; 以及DLL电路，用于通过使用第三内部时钟信号输出延迟锁定时钟信号。

公开(公告)号：US07720182B2

公开(公告)日：2010-05-18

申请号：US11636243

申请日：2006-12-08

Applicant: Tae-Hoon Kim ,  Pan-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh ,  Seong-Jun Lee

Inventor： Tae-Hoon Kim ,  Pan-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh ,  Seong-Jun Lee

IPC: H04L1/00

CPC classification number: H04B7/18523 ,  H04L27/2657 ,  H04L27/2672 ,  H04L27/2676

Abstract: An apparatus and method for correcting a frequency offset in a satellite digital video broadcasting system includes a frequency response transformer for receiving a satellite digital video broadcasting signal and acquiring frequency responses divided into positive and negative frequency parts; a rotation/difference value calculation unit for selecting a frequency response inputted from the frequency response transformer and calculating a first value indicating a difference in area without rotation for the selected frequency response, and calculating a second value indicating a difference in area with rotation for the remaining frequency responses; a zero intersection point calculator for dividing an average slope of a straight line formed by the first and second values by the first value, and calculating a zero intersection point of an area difference value on the straight line; and a frequency offset estimator for correcting the zero intersection point to thereby estimate the frequency offset.

Abstract translation: 一种用于校正卫星数字视频广播系统中的频率偏移的装置和方法包括：频率响应变换器，用于接收卫星数字视频广播信号并获取被分为正，负频率部分的频率响应; 旋转/差值计算单元，用于选择从频率响应变换器输入的频率响应，并计算指示所选择的频率响应的不旋转的面积差的第一值，并且计算表示针对所选择的频率响应的旋转区域的差异的第二值 剩余频率响应; 零交叉点计算器，用于将由第一和第二值形成的直线的平均斜率除以第一值，并计算直线上面积差值的零交叉点; 以及用于校正零交叉点从而估计频率偏移的频率偏移估计器。

公开(公告)号：US20100109727A1

公开(公告)日：2010-05-06

申请号：US12493712

申请日：2009-06-29

Applicant: Seong-Jun Lee

Inventor： Seong-Jun Lee

IPC: H03L7/06

CPC classification number: H03L7/0812

Abstract: A semiconductor device for providing a reliable data valid window includes a drive control unit configured to output a driving power control signal in response to an internal clock and a command signal; a sub-drive voltage supply unit configured to supply sub-drive voltages; a main drive unit configured to generate a delay-locked loop (DLL) clock by driving the internal clock with a main drive voltage; a sub-drive unit configured to drive the internal clock with the sub-drive voltage in response to the driving power control signal; and a data output driver configured to drive and output a data signal in sync with the DLL clock, wherein the main drive unit and the sub-drive unit share their output terminal.

Abstract translation: 用于提供可靠数据有效窗口的半导体器件包括：驱动控制单元，被配置为响应于内部时钟和命令信号输出驱动功率控制信号; 副驱动电压供给部，被配置为提供副驱动电压; 主驱动单元，被配置为通过以主驱动电压驱动内部时钟来产生延迟锁定环（DLL）时钟; 子驱动单元，被配置为响应于驱动功率控制信号而以副驱动电压驱动内部时钟; 以及数据输出驱动器，被配置为与DLL时钟同步地驱动和输出数据信号，其中主驱动单元和副驱动单元共享其输出端子。

公开(公告)号：US20080136479A1

公开(公告)日：2008-06-12

申请号：US11647645

申请日：2006-12-29

Applicant: Min-Young You ,  Seong-Jun Lee

Inventor： Min-Young You ,  Seong-Jun Lee

IPC: H03L7/00

CPC classification number: H03L7/0812 ,  G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  H03K5/1565

Abstract: A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.

Abstract translation: 半导体存储器件包括：第一时钟缓冲器，用于响应于系统时钟信号的反相信号输出第一内部时钟信号，并用于响应于控制信号来校正第一内部时钟信号的占空比; 第二时钟缓冲器，用于响应于所述系统时钟信号输出第二内部时钟信号，并用于响应于所述控制信号来校正所述第二内部时钟信号的占空比; 模拟占空比校正电路，用于输出对应于第一和第二内部时钟信号的占空比的控制信号; 混合电路，用于混合第一和第二内部时钟信号，并输出其占空比被校正的第三内部时钟信号; 以及DLL电路，用于通过使用第三内部时钟信号输出延迟锁定时钟信号。

公开(公告)号：US20080100353A1

公开(公告)日：2008-05-01

申请号：US11819811

申请日：2007-06-29

Applicant: Seong-Jun Lee ,  Min-Young You

Inventor： Seong-Jun Lee ,  Min-Young You

IPC: H03L7/06

CPC classification number: H03L7/0814

Abstract: A delay locked loop includes a buffer for outputting an internal clock by buffering an external clock, a delay block for delaying the internal clock in response to one of control signals or a selection signal, thereby outputting a delayed clock, a control signal generation block for generating at least one control signal according to a phase difference between the internal clock and a feedback clock generated by delaying the delayed clock by a delay time taken for the internal clock to be output, a selection block for outputting at least one selection signal in response to a signal instructing an off mode of the delay locked loop, thereby controlling a delay time in the delay block, and an output driver for driving the delayed clock.

Abstract translation: 延迟锁定环包括缓冲器，用于通过缓冲外部时钟来输出内部时钟;延迟块，用于响应于控制信号之一或选择信号延迟内部时钟，从而输出延迟的时钟;控制信号产生块，用于 根据内部时钟与通过延迟延迟时钟产生的反馈时钟之间的相位差产生至少一个控制信号，所述延迟时间将被输出用于输出内部时钟的延迟时间;响应于输出至少一个选择信号的选择块 指示延迟锁定环的关闭模式的信号，从而控制延迟块中的延迟时间，以及用于驱动延迟时钟的输出驱动器。

公开(公告)号：US20070195256A1

公开(公告)日：2007-08-23

申请号：US11676743

申请日：2007-02-20

Applicant: Seong-Jun Lee ,  Jin Jeon ,  Yong-Je Jeon ,  Sung-In Ro ,  Sun-Ja Kwon ,  Sang-Ho Moon

Inventor： Seong-Jun Lee ,  Jin Jeon ,  Yong-Je Jeon ,  Sung-In Ro ,  Sun-Ja Kwon ,  Sang-Ho Moon

IPC: G02F1/1339

CPC classification number: G02F1/1339 ,  G02F1/133351 ,  G02F1/13454

Abstract: A liquid crystal display (LCD) apparatus and a method of manufacturing the same include a seal line having two protrusions, one of the protrusions having a liquid crystal (LC) injection hole. Moreover, the LCD apparatus having the seal line constitutes a closed loop. The display apparatus and the manufacturing method thereof increase production yields because the number of apparatus substrates for the display apparatus obtained from a mother substrate is increased by minimizing a distance between two adjacent apparatus substrates on the mother substrate. The method of manufacturing an exemplary LCD apparatus includes a one drop filling method or a vacuum injection method.

Abstract translation: 液晶显示（LCD）装置及其制造方法包括具有两个突起的密封线，一个突起具有液晶（LC）注入孔。 此外，具有密封线的LCD装置构成闭环。 由于通过使母基板上两个相邻的装置基板之间的距离最小化来增加从母基板获得的用于显示装置的装置基板的数量，所以显示装置及其制造方法增加了产量。 制造示例性LCD装置的方法包括一滴灌装法或真空注入法。

公开(公告)号：US08902388B2

公开(公告)日：2014-12-02

申请号：US12635258

申请日：2009-12-10

Applicant: Yong-Kyu Jang ,  Jae-Young Lee ,  Seong-Jun Lee ,  Yi Li

Inventor： Yong-Kyu Jang ,  Jae-Young Lee ,  Seong-Jun Lee ,  Yi Li

IPC: G02F1/1335 ,  G02F1/1333 ,  G02F1/141 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1337 ,  G02F1/139 ,  G02F1/137

CPC classification number: G02F1/136227 ,  G02F1/133707 ,  G02F1/1393 ,  G02F2001/133746 ,  G02F2001/13775

Abstract: A display device may include a first substrate, a second substrate, and a liquid crystal layer. The first substrate may include a domain-forming layer including a depression pattern for forming a liquid crystal domain in a pixel area and a pixel electrode formed on the domain-forming layer. The second substrate may face the first substrate. The second substrate may include a common electrode formed on the entire surface thereof. The liquid crystal layer may be disposed between the first substrate and the second substrate. The liquid crystal layer may include a reactive mesogen (RM) which fixes liquid crystal molecules formed in the liquid crystal domain. Since a liquid crystal domain may be formed without a separate pattern on a common electrode, a display device having an enhanced aperture ratio and an enhanced viewing angle may be manufactured.

Abstract translation: 显示装置可以包括第一基板，第二基板和液晶层。 第一基板可以包括域形成层，其包括用于在像素区域中形成液晶畴的凹陷图案和形成在畴形成层上的像素电极。 第二基板可面向第一基板。 第二基板可以包括在其整个表面上形成的公共电极。 液晶层可以设置在第一基板和第二基板之间。 液晶层可以包括固定液晶畴中形成的液晶分子的反应性液晶元（RM）。 由于可以在公共电极上形成没有单独图案的液晶畴，因此可以制造具有增大的开口率和增强的视角的显示装置。

公开(公告)号：US08896792B2

公开(公告)日：2014-11-25

申请号：US13046069

申请日：2011-03-11

Applicant: Jae-Young Lee ,  Seong-Jun Lee ,  Yi Li ,  Ju-Yeon Seo

Inventor： Jae-Young Lee ,  Seong-Jun Lee ,  Yi Li ,  Ju-Yeon Seo

IPC: G02F1/141 ,  C09K19/02 ,  G02F1/1337

CPC classification number: G02F1/133707 ,  G02F1/133711 ,  G02F1/133753 ,  G02F2001/133726 ,  G02F2001/133776

Abstract: A display device that prevents occurrence of a phenomenon where a boundary portion of a pixel region becomes dark, and a method of manufacturing the same. The display device includes a first substrate arrangement including a domain forming layer having a depression pattern for forming a liquid crystal domain in a pixel region, and a pixel electrode arranged on the domain forming layer, a second substrate arrangement including a common electrode arranged on an entire surface facing the first substrate arrangement, a liquid crystal layer arranged between the first and second substrate arrangements and including a plurality of liquid crystal molecules and a reactive mesogen (RM) to fix the liquid crystal molecules to form the liquid crystal domain, a sealant arranged between the first and second substrate arrangements to adhere the first and second substrate arrangement together and a light blocker arranged between the sealant and the liquid crystal layer to block light incident from an external side of the sealant.

Abstract translation: 一种防止像素区域的边界部分变暗的现象发生的显示装置及其制造方法。 显示装置包括：第一基板装置，包括具有用于在像素区域中形成液晶畴的凹陷图案的区域形成层和布置在畴形成层上的像素电极;第二基板装置，包括布置在 面对第一基板布置的整个表面，布置在第一和第二基板布置之间并且包括多个液晶分子和反应性液晶元（RM）的液晶层以固定液晶分子以形成液晶畴，密封剂 布置在第一和第二基板布置之间以将第一和第二基板布置在一起，以及设置在密封剂和液晶层之间的阻光剂，以阻挡从密封剂的外侧入射的光。

公开(公告)号：US08570473B2

公开(公告)日：2013-10-29

申请号：US12537595

申请日：2009-08-07

Applicant: Yi Li ,  Seong-Jun Lee ,  Jae-Young Lee ,  Seon-Hong Ahn ,  Sung-Hoon Kim

Inventor： Yi Li ,  Seong-Jun Lee ,  Jae-Young Lee ,  Seon-Hong Ahn ,  Sung-Hoon Kim

IPC: G02F1/1337

CPC classification number: G02F1/134309 ,  G02F1/133707 ,  G02F2001/133726 ,  G02F2001/134345 ,  G02F2201/40

Abstract: A display substrate includes a base substrate on which a pixel area is defined. The pixel area includes a first sub-pixel area and a second sub-pixel area. A plurality of first electrode portions is disposed at a first interval in the first sub-pixel area, and a plurality of second electrode portions is disposed at a second interval in the second sub-pixel area. The first electrode portion has a first width, and the second electrode portion has a second width. The first width of the first electrode portion is different from the second width of the second electrode portion, or the first interval between adjacent first electrode portions is different from the second interval between adjacent second electrode portions.

Abstract translation: 显示基板包括其上限定像素区域的基底基板。 像素区域包括第一子像素区域和第二子像素区域。 多个第一电极部分在第一子像素区域中以第一间隔设置，并且多个第二电极部分以第二间隔设置在第二子像素区域中。 第一电极部分具有第一宽度，第二电极部分具有第二宽度。 第一电极部分的第一宽度不同于第二电极部分的第二宽度，或者相邻的第一电极部分之间的第一间隔与相邻的第二电极部分之间的第二间隔不同。