公开(公告)号：US20200185425A1

公开(公告)日：2020-06-11

申请号：US16613873

申请日：2018-05-11

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Teruyuki UEDA ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Toshikatsu ITOH

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1343

Abstract: Each of pixel regions of an active matrix substrate (1002) includes: a lower insulating layer (5); an oxide semiconductor layer (7) that is arranged on the lower insulating layer and includes an active region (7a) of an oxide semiconductor TFT; an upper insulating layer (9) that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer (10) that is arranged on the upper insulating layer and includes an upper gate electrode (10a) and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layer 7 further includes an extension region (7e) that extends from the active region (7a) in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region (7e) is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer (9) interposed therebetween, and includes a portion that extends so as to overlap with the one of the plurality of gate bus lines.

公开(公告)号：US20200183208A1

公开(公告)日：2020-06-11

申请号：US16084570

申请日：2017-03-13

Applicant: Sharp Kabushiki Kaisha

Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Hajime IMAI ,  Toshikatsu ITOH ,  Hisao OCHI ,  Hideki KITAGAWA ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Ryosuke GUNJI ,  Kengo HARA ,  Setsuji NISHIMIYA

IPC: G02F1/1368 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1362

Abstract: Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).

公开(公告)号：US20200073189A1

公开(公告)日：2020-03-05

申请号：US16548886

申请日：2019-08-23

Applicant: Sharp Kabushiki Kaisha

Inventor： Hitoshi TAKAHATA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Kengo HARA ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Yoshihito HARA

IPC: G02F1/1362 ,  H01L27/12 ,  H01L27/32

Abstract: [Object]To provide an active matrix substrate (1) that includes an organic insulating film (OIL) and first source layers (FSL2 to FSL4) and second source layers (SSL1 to SSL3), which constitute two-layer wiring lines, and that is produced with a high yield.[Solution]In an active matrix substrate (1), of the first source layers (FSL2 to FSL4) and the second source layers (SSL1 to SSL3), the second source layers (SSL1 to SSL3) arranged further from the substrate (2) are in contact with an organic insulating film (OIL) with a second inorganic insulating film (SINOIL) interposed therebetween.

公开(公告)号：US20200043955A1

公开(公告)日：2020-02-06

申请号：US16515057

申请日：2019-07-18

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Kengo HARA

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362

Abstract: A semiconductor device includes a first TFT, a first source-side connection section that is formed from a part of a second metal film and connected to a first source region, a first drain-side connection section that is formed from a part of the second metal film and connected to a first drain region, a second TFT that is driven by the first TFT, a second source-side connection section that is formed from a part of a first metal film and connected to a second source region, and a second drain-side connection section that is formed from a part of the first metal film or a second transparent electrode film and connected to a second drain region.

公开(公告)号：US20200035717A1

公开(公告)日：2020-01-30

申请号：US16508603

申请日：2019-07-11

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA

IPC: H01L27/12 ,  H01L29/786

Abstract: A thin film transistor substrate includes a source line, a gate electrode, a channel region, a source region, a drain region, and a pixel electrode. The gate electrode is a portion of a first metal film disposed upper than a first insulating film that is disposed upper than a semiconductor film. The source line is a portion of a second metal film disposed upper than a second insulating film that is disposed upper than the first metal film. The channel region is a portion of a section of the semiconductor film and disposed to overlap the gate electrode. The source region is prepared by reducing a resistance of a section of the semiconductor film. The drain region is prepared by reducing a resistance of a section of the semiconductor film. The pixel electrode is prepared by reducing a resistance of a section of the semiconductor film.

公开(公告)号：US20200027958A1

公开(公告)日：2020-01-23

申请号：US16497893

申请日：2018-03-23

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Toshikatsu ITOH ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA ,  Hajime IMAI ,  Tohru DAITOH

IPC: H01L29/49 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/24 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.

公开(公告)号：US20200020756A1

公开(公告)日：2020-01-16

申请号：US16496969

申请日：2018-03-19

Applicant: Sharp Kabushiki Kaisha

Inventor： Teruyuki UEDA ,  Hideki KITAGAWA ,  Tohru DAITOH ,  Hajime IMAI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Tetsuo KIKUCHI ,  Toshikatsu ITOH ,  Kengo HARA

IPC: H01L27/32 ,  G02F1/1362

Abstract: An oxide semiconductor TFT (201) of an active matrix substrate includes an oxide semiconductor layer (107), an upper gate electrode (112) disposed on a part of the oxide semiconductor layer via a gate insulating layer, and a source electrode (113) and a drain electrode (114). As viewed from a normal direction of the substrate, the oxide semiconductor layer (107) includes a first portion (p1) that overlaps the upper gate electrode, and a second portion (p2) that is located between the first portion and the source contact region or drain contact region, such that the gate insulating layer does not cover the second portion. The upper gate electrode (112) has a multilayer structure including an alloy layer (112L) that is in contact with the gate insulating layer and a metal layer (112U) that is disposed on the alloy layer. The metal layer is made of a first metallic element M; the alloy layer is made of an alloy containing the first metallic element M; and the first metallic element M is Cu, Mo, or Cr.

公开(公告)号：US20240339460A1

公开(公告)日：2024-10-10

申请号：US18746280

申请日：2024-06-18

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L29/78633 ,  H01L29/7869

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

公开(公告)号：US20240297181A1

公开(公告)日：2024-09-05

申请号：US18663479

申请日：2024-05-14

Applicant: Sharp Kabushiki Kaisha

Inventor： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1237 ,  H01L27/127 ,  H01L29/7869 ,  H01L29/78696

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

公开(公告)号：US20230215877A1

公开(公告)日：2023-07-06

申请号：US18119629

申请日：2023-03-09

Applicant: Sharp Kabushiki Kaisha

Inventor： Kengo HARA ,  Tohru DAITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Hitoshi TAKAHATA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L29/78633 ,  H01L29/7869

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.