公开(公告)号：US06246724B1

公开(公告)日：2001-06-12

申请号：US09533982

申请日：2000-03-23

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H04L2534

CPC分类号： H04L5/20 ,  H04L25/49

摘要： A signal transfer method for transferring a multi-bit signal over a transfer path which is allocated to one bit includes the steps of: respectively assigning a plurality of parameters for a plurality of bits so that a value representing “0” or a value representing “1” is set to each of the plurality of parameters in accordance with a value of a corresponding one of the plurality of bits; outputting an electric signal to the transfer path, the electric signal expressing a combination of the plurality of parameters having the values as set in the assigning step; receiving the electric signal from the transfer path and extracting the plurality of parameters from the electric signal; and detecting the respective values of the plurality of parameters.

摘要翻译： 用于通过分配给一位的传送路径传送多位信号的信号传送方法包括以下步骤：分别分配多个比特的多个参数，使得表示“0”的值或表示“ 1“根据多个比特中的相应一个比特的值被设置为多个参数中的每一个; 向所述传送路径输出电信号，所述电信号表示具有在所述分配步骤中设定的值的所述多个参数的组合; 从传输路径接收电信号并从电信号中提取多个参数; 以及检测所述多个参数的相应值。

公开(公告)号：US06208567B1

公开(公告)日：2001-03-27

申请号：US09014775

申请日：1998-01-28

申请人： Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Toru Iwata ,  Keiichi Kusumoto ,  Satoshi Takahashi ,  Yutaka Terada ,  Takashi Hirata

发明人： Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Toru Iwata ,  Keiichi Kusumoto ,  Satoshi Takahashi ,  Yutaka Terada ,  Takashi Hirata

IPC分类号： G11C2900

CPC分类号： G01R31/3004 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.

摘要翻译： 本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

公开(公告)号：US06194926B1

公开(公告)日：2001-02-27

申请号：US09291173

申请日：1999-04-14

申请人： Satoshi Takahashi ,  Hiroyuki Yamauchi

发明人： Satoshi Takahashi ,  Hiroyuki Yamauchi

IPC分类号： H03L700

CPC分类号： H03L7/00 ,  G06F1/04

摘要： A system of the type including a plurality of circuit blocks is provided with an operation timing controller for controlling the operation timing of these circuit blocks by supplying associated operation control signals thereto. The operation timing controller includes a memory for memorizing respective times when a peak current state arises in these circuit blocks, thereby controlling the timing of the operation control signals in accordance with the memorized times when the peak current state arises. As a result, coincident switching noise can be suppressed no matter when the peak current state arises in these circuit blocks.

摘要翻译： 包括多个电路块的类型的系统设置有操作定时控制器，用于通过向其提供相关联的操作控制信号来控制这些电路块的操作定时。 操作定时控制器包括用于在这些电路块中出现峰值电流状态时存储各个时间的存储器，从而根据当峰值电流状态出现时的存储时间来控制操作控制信号的定时。 结果，无论何时在这些电路块中出现峰值电流状态，也可以抑制一致的开关噪声。

公开(公告)号：US6127950A

公开(公告)日：2000-10-03

申请号：US244764

申请日：1999-02-05

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H03M7/00

CPC分类号： H03M5/145

摘要： Image data is transmitted from a memory to a CPU (central processing unit). A transmission circuit of the memory receives an 8-bit source parallel signal, makes reference to transmission histories or to transmission predictions to generate a 2-bit coded parallel signal from the source parallel signal, and sends a serial signal as a result of converting the coded parallel signal, together with a flag signal indicative of the presence of an encoding. If the source parallel signal remains unchanged, the coded parallel signal is made to indicate 00 so that the bit transition probability of the serial signal is reduced. A reception circuit of the CPU receives the serial and flag signals and restores the 8-bit source parallel signal on the basis of reception histories or on the basis of reception predictions. If the transmission circuit fails in performing an encoding, then a serial signal as a result of directly converting the source parallel signal is sent together with a flag signal indicative of the absence of an encoding.

摘要翻译： 图像数据从存储器发送到CPU（中央处理单元）。 存储器的发送电路接收8位源并行信号，参照发送历史或发送预测，从源并行信号生成2比特编码并行信号，作为转换结果的结果发送串行信号 编码并行信号，以及指示编码存在的标志信号。 如果源并行信号保持不变，则将编码的并行信号指示为00，使得串行信号的位转移概率减小。 CPU的接收电路接收串行和标志信号，并根据接收历史或基于接收预测恢复8位源并行信号。 如果发送电路执行编码失败，则作为直接转换源并行信号的结果的串行信号与指示不存在编码的标志信号一起发送。

公开(公告)号：US5999022A

公开(公告)日：1999-12-07

申请号：US631914

申请日：1996-04-15

申请人： Toru Iwata ,  Hironori Akamatsu ,  Hisakazu Kotani ,  Hiroyuki Yamauchi ,  Akira Matsuzawa ,  Shoichiro Tada

发明人： Toru Iwata ,  Hironori Akamatsu ,  Hisakazu Kotani ,  Hiroyuki Yamauchi ,  Akira Matsuzawa ,  Shoichiro Tada

IPC分类号： H03K19/00 ,  H03K19/0185 ,  H03K3/00

CPC分类号： H03K19/01855 ,  H03K19/0016

摘要： A driver circuit which drives a signal line includes a first output section for outputting a reference voltage potential to the signal line during a first period and a second output section for outputting one of a first information voltage potential and a second information voltage potential in accordance with an input signal during a second period.

摘要翻译： 驱动信号线的驱动器电路包括：第一输出部，用于在第一时段期间向信号线输出参考电压电位;以及第二输出部，用于输出第一信息电压电位和第二信息电压电位之一 在第二时段期间的输入信号。

公开(公告)号：US5757702A

公开(公告)日：1998-05-26

申请号：US739363

申请日：1996-10-29

申请人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

发明人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C11/419 ,  G11C11/412

摘要： A memory cell includes a first inverter and a second inverter connected with each other through the output node of one of the inverters and the input node of the other inverter, and first and second transistors. Each of the transistors connected with a word line at its gate electrode is interposed between one of a bit line pair and each memory node. This data holding circuit includes an element for increasing a memory cell supply potential for driving the pair of inverters to be higher than a supply potential applied to peripheral circuits, or an element for decreasing a ground voltage for driving the pair of inverters to be lower than a ground voltage applied to the peripheral circuits.

摘要翻译： 存储单元包括通过其中一个反相器的输出节点和另一个反相器的输入节点以及第一和第二晶体管彼此连接的第一反相器和第二反相器。 在其栅电极处与字线连接的晶体管中的每一个插入在位线对和每个存储器节点之一之间。 该数据保持电路包括用于将用于驱动该对反相器的存储单元电源电位增加到高于施加到外围电路的电源电位的元件，或者用于将用于驱动该对反相器的接地电压降低到低于 施加到外围电路的接地电压。

公开(公告)号：US5689469A

公开(公告)日：1997-11-18

申请号：US742537

申请日：1996-11-01

申请人： Hideo Asaka ,  Hiroyuki Yamauchi

发明人： Hideo Asaka ,  Hiroyuki Yamauchi

IPC分类号： G11C8/08 ,  G11C11/408 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/4085 ,  G11C29/02 ,  G11C29/50 ,  G11C8/08 ,  G11C11/401

摘要： Precharge circuits precharge plural pairs of bit lines to a specified potential when no word line is selected (during standby). Pull-down transistors are turned ON when the corresponding word lines are not selected so as to connect the corresponding word lines to a common power source line, which is connected to the ground. In a path connecting the above common power source line to the ground is disposed an impedance changing means for changing the impedance of the path between a value during standby and another value during operation during which any word line is selected so that the value during standby is set higher than the value during operation. Consequently, during standby, a leakage current (standby current) resulting from a short circuit between a bit line and a word line is reduced.

摘要翻译： 当没有选择字线（待机）时，预充电电路将多对位线预充电到指定的电位。 当对应的字线未被选择时，下拉晶体管导通，以将相应的字线连接到连接到地的公共电源线。 在将上述公共电源线连接到地线的路径中设置有阻抗改变装置，用于改变在待机期间的值之间的路径的阻抗和在其中选择任何字线的操作期间的另一个值，使得待机期间的值为 设置高于操作期间的值。 因此，在待机期间，由位线和字线之间的短路引起的漏电流（待机电流）减小。

公开(公告)号：US5450139A

公开(公告)日：1995-09-12

申请号：US168230

申请日：1993-12-17

申请人： Hideo Haraguchi ,  Kaichi Tatsuzawa ,  Hiroyuki Yamauchi

发明人： Hideo Haraguchi ,  Kaichi Tatsuzawa ,  Hiroyuki Yamauchi

IPC分类号： H04N5/268 ,  H04N5/222

CPC分类号： H04N5/222 ,  H04H60/06 ,  H04H60/27

摘要： Apparatus for transmitting video signals includes a primary storage device having a plurality of storage units for storing and reading video signals selectively supplied thereto by a coupling circuit. An alternate storage device functions as a backup and receives and stores all of the video signals that are supplied to the primary storage device; and reads out therefrom the video signals which are in the process of being read from the primary storage device in the event a failure is detected in the primary storage device.

摘要翻译： 用于发送视频信号的设备包括具有多个存储单元的主存储设备，用于存储和读取由耦合电路选择性地提供给其的视频信号。 备用存储设备用作备份，并接收并存储提供给主存储设备的所有视频信号; 并且在主存储装置中检测到故障的情况下读出正在从主存储装置读取的视频信号。

公开(公告)号：US5389810A

公开(公告)日：1995-02-14

申请号：US35731

申请日：1993-03-23

申请人： Masashi Agata ,  Hiroyuki Yamauchi ,  Toshio Yamada

发明人： Masashi Agata ,  Hiroyuki Yamauchi ,  Toshio Yamada

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L27/088

摘要： A semiconductor device having at least one symmetrical pair of MOSFETs is provided. The device includes a semiconductor layer having an upper surface, an active region formed in the upper surface, an isolation region formed in the upper surface and enclosing the active region, and a pair of MOSFETs formed in the active region, wherein the pair of MOSFETs are symmetrical with respect to a first symmetric plane substantially vertical to the upper surface and also with respect to a second symmetric plane vertical both to the upper surface and to the first symmetric plane, each of the pair of MOSFETs includes a source region, a drain region, and a channel region formed in an upper surface of the active region, the source region is shared by the pair of MOSFETs, and the drain region is spatially isolated from the source region by the channel region.

摘要翻译： 提供了具有至少一对对称的MOSFET的半导体器件。 该器件包括具有上表面的半导体层，形成在上表面中的有源区，形成在上表面并包围有源区的隔离区，以及形成在有源区中的一对MOSFET，其中，所述一对MOSFET 相对于基本上垂直于上表面的第一对称平面以及垂直于上表面和第一对称平面的第二对称平面是对称的，所述一对MOSFET中的每一个包括源极区域，漏极 区域和形成在有源区的上表面中的沟道区域，源极区域被该对MOSFET共享，并且漏极区域通过沟道区域与源极区域空间隔离。

公开(公告)号：US07453359B2

公开(公告)日：2008-11-18

申请号：US11000206

申请日：2004-12-01

申请人： Toshio Watanabe ,  Hiroyuki Yamauchi

发明人： Toshio Watanabe ,  Hiroyuki Yamauchi

IPC分类号： G08B13/14

CPC分类号： G06K19/07771 ,  G06K7/10178 ,  G06K7/10336

摘要： An IC tag communication relay device is provided with an antenna section, lead lines and input/output unit. The antenna section is equipped with one or more antennas for transmitting and receiving electromagnetic radiation to and from IC tags. The lead lines are connected to each antenna for transmitting electrical signals corresponding to transmitted and received electromagnetic radiation. The input/output unit is arranged outside of the antenna corresponding to each antenna connected to the lead lines.

摘要翻译： IC标签通信中继装置设置有天线部分，引线和输入/输出单元。 天线部分配备有一个或多个天线，用于向IC标签发送和接收电磁辐射。 导线连接到每个天线，用于发送对应于发射和接收的电磁辐射的电信号。 输入/输出单元布置在与连接到引线的每个天线对应的天线的外部。