公开(公告)号：US20100034026A1

公开(公告)日：2010-02-11

申请号：US12535903

申请日：2009-08-05

申请人： Shoichi Kawamura

发明人： Shoichi Kawamura

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/344 ,  G11C16/14 ,  G11C16/16

摘要： An erase method for a non-volatile memory device having a defined erase unit divided into first and second inner erase units includes; applying an erase voltage to at least one of the first and second inner erase units in accordance with respective states of corresponding first and second fail flags, after applying the erase voltage to the at least one of the first and second inner erase units, performing an erase verification on the at least one of the first and second inner erase units, and updating the at least one of the first and second fail flags in accordance with erase verification results.

摘要翻译： 具有划分为第一和第二内部擦除单元的限定的擦除单元的非易失性存储器件的擦除方法包括： 在将擦除电压施加到第一和第二内部擦除单元中的至少一个之后，根据相应的第一和第二故障标志的相应状态，向第一和第二内部擦除单元中的至少一个施加擦除电压， 在第一和第二内部擦除单元中的至少一个擦除验证，以及根据擦除验证结果更新第一和第二失败标志中的至少一个。

公开(公告)号：US07499318B2

公开(公告)日：2009-03-03

申请号：US11612173

申请日：2006-12-18

申请人： Kazunari Kido ,  Shoichi Kawamura

发明人： Kazunari Kido ,  Shoichi Kawamura

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C16/24

摘要： A nonvolatile semiconductor memory device has a high read output and is not affected by a noise of adjacent bit lines. The memory device is capable of performing high speed read operations. Each bit of a memory as formed by a plurality of memory cells. The memory cells each have the same structure as the structure of a memory cell of the main memory. During a read operation, the bit line is selected and proximate bit lines proximate to the selected bit line are not selected. The nonvolatile semiconductor memory device is formed together with the main memory on one chip by the same process.

摘要翻译： 非易失性半导体存储器件具有高读取输出并且不受相邻位线的噪声的影响。 存储器件能够进行高速读取操作。 由多个存储单元形成的存储器的每一位。 每个存储单元具有与主存储器的存储单元的结构相同的结构。 在读操作期间，选择位线，并且不选择靠近所选位线的位线。 非易失性半导体存储器件通过相同的工艺与主存储器一起形成在一个芯片上。

公开(公告)号：US06747894B2

公开(公告)日：2004-06-08

申请号：US10299756

申请日：2002-11-20

申请人： Shoichi Kawamura

发明人： Shoichi Kawamura

IPC分类号： G11C1600

CPC分类号： G11C29/021 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/28 ,  G11C29/028 ,  G11C29/50004 ,  G11C2211/5634

摘要： First and second memory units store reference values and verification values for generating reference voltages and verification voltages of nonvolatile multilevel memory cells. A reference voltage generator generates the reference voltages and the verification voltages according to the reference values and the verification values stored in the first and second memory units. Since the first and second memory units are rewritable, the reference voltages and the verification voltages can be set after the fabrication of the cell memory in accordance with the characteristics of the memory cells which are dependent on variations of fabrication process. A programming test circuit for obtaining the reference voltages and the verification voltages can also be used to set the reference voltages and the verification voltages after the fabrication of the cell memory. Consequently, it is possible to improve the read margins of data read from the memory cells with an enhancement in fabrication yield.

摘要翻译： 第一和第二存储单元存储用于产生非易失性多电平存储单元的参考电压和验证电压的参考值和验证值。 参考电压发生器根据存储在第一和第二存储器单元中的参考值和验证值产生参考电压和验证电压。 由于第一和第二存储器单元是可重写的，所以可以根据依赖于制造工艺的变化的存储器单元的特性来在单元存储器的制造之后设置参考电压和验证电压。 用于获得参考电压和验证电压的编程测试电路也可用于在单元存储器制造之后设置参考电压和验证电压。 因此，随着制造成品率的提高，可以提高从存储器单元读取的数据的读取余量。

公开(公告)号：US06670669B1

公开(公告)日：2003-12-30

申请号：US10030117

申请日：2002-01-23

申请人： Shoichi Kawamura

发明人： Shoichi Kawamura

IPC分类号： H01L2976

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

摘要： The invention is to provide a novel non-volatile memory capable of recording multi-bit data. The invention is a non-volatile memory which has: first and second source-drain regions SD1, SD2 at the surface of a semiconductor substrate; and a non-conductive trapping gate TG, and a conductive control gate CG, formed on a channel region there between via an insulating film. Further, the non-volatile memory has a first or second state in which, by applying a voltage between the first and second source-drain regions SD1, SD2, hot electrons produced in the vicinity of the first or second source-drain region are locally captured in a first or second trapping gate region TSD1, TSD2 in the vicinity of them; and, a third state in which, by applying a voltage between the control gate and the channel region, electrons (or charge) are (is) injected into the entire trapping gate. According to whether or not the above-mentioned third state is adopted, one-bit information can be recorded, and according to whether or not the first and second states are adopted, two-bit information can be recorded. Consequently, information totaling three bits can be recorded in a single memory cell.

摘要翻译： 本发明提供一种能够记录多位数据的新型非易失性存储器。 本发明是一种非易失性存储器，其在半导体衬底的表面具有：第一和第二源极 - 漏极区域SD1，SD2; 以及通过绝缘膜形成在其间的沟道区域上的非导电捕获栅极TG和导电控制栅极CG。 此外，非易失性存储器具有第一或第二状态，其中通过在第一和第二源极 - 漏极区域SD1，SD2之间施加电压，在第一或第二源极 - 漏极区域附近产生的热电子是局部的 捕获在它们附近的第一或第二捕获栅区TSD1，TSD2中; 并且通过在控制栅极和沟道区域之间施加电压，将电子（或电荷）注入到整个捕获栅极中的第三状态。 根据是否采用上述第三状态，可以记录一位信息，并且根据是否采用第一和第二状态，可以记录2位信息。 因此，总共三位的信息可以记录在单个存储单元中。

公开(公告)号：US06259630B1

公开(公告)日：2001-07-10

申请号：US09541687

申请日：2000-04-03

申请人： Shoichi Kawamura

发明人： Shoichi Kawamura

IPC分类号： G11C1634

CPC分类号： G11C16/3445 ,  G11C16/3436 ,  G11C16/3459 ,  G11C2216/14

摘要： A nonvolatile semiconductor memory device has an array of memory cells in columns and rows, and has word lines and bit lines provided in orthogonal directions, the memory cells for each column sharing one of the bit lines, and the memory cells for each row sharing one of the word lines. The memory device includes a plurality of subblocks of N page buffers where N is a given positive integer, the N page buffers for each subblock temporarily storing data bits that are written to or erased from N memory cells at a time in the memory array in response to a selected one of the word lines. A verify/output circuit produces, in response to signals output by the plurality of subblocks of N page buffers, a verify status of each of the respective subblocks that indicates whether the data bits are properly written to or erased from the N memory cells, the verify/output circuit outputting the verify status of at least one of the plurality of subblocks to an external device.

摘要翻译： 非易失性半导体存储器件具有列和行中的存储单元的阵列，并且具有在正交方向上提供的字线和位线，每个列的共享一个位线的存储器单元以及每行的存储单元共享一个 的字线。 存储器件包括N页缓冲器的多个子块，其中N是给定的正整数，每个子块的N页缓冲器临时存储在存储器阵列中一次从N个存储器单元写入或擦除的数据位，作为响应 到选定的一行字线。 验证/输出电路响应于N页缓冲器的多个子块输出的信号，产生指示数据位是否被正确写入或从N个存储器单元擦除的每个子块的校验状态， 验证/输出电路将多个子块中的至少一个子块的验证状态输出到外部设备。

公开(公告)号：US20110157960A1

公开(公告)日：2011-06-30

申请号：US12974809

申请日：2010-12-21

申请人： Shoichi Kawamura

发明人： Shoichi Kawamura

IPC分类号： G11C11/00 ,  G11C11/36 ,  G11C8/08

CPC分类号： G11C13/0028 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/004 ,  G11C2213/71 ,  G11C2213/72

摘要： Nonvolatile memory devices are provided including a memory cell array having a plurality of stacked memory layers and a rectifier configured to select memory cells constituting each memory layer sharing a word line or a bit line with another adjacent memory layer. The nonvolatile memory devices including a word line driving unit configured to drive a first word line, connected to a first memory cell of a first memory layer to be read, at a first voltage level and drive a second word line, connected to a second memory cell of a second memory layer sharing a first bit line connected to the first memory cell, at a second voltage level. The nonvolatile memory device further includes a bit line biasing unit configured to bias the first bit line at the second voltage level and bias a second bit line, connected to a third memory cell of a third memory layer sharing the first word line, at the first voltage level. Related methods and systems are also provided herein.

摘要翻译： 提供了非易失性存储器件，其包括具有多个堆叠存储器层的存储单元阵列和被配置为选择与另一个相邻存储层共享字线或位线的每个存储器层的存储单元的整流器。 所述非易失性存储器件包括字线驱动单元，被配置为驱动第一字线，连接到第一存储器单元，所述第一字线连接到待读取的第一存储器层的第一电压电平并驱动第二字线，所述第二字线连接到第二存储器 在第二电压电平下共享连接到第一存储器单元的第一位线的第二存储器层的单元。 非易失性存储器件还包括位线偏置单元，其被配置为在第二电压电平处偏置第一位线，并且在第一电压电平处偏置连接到共享第一字线的第三存储器层的第三存储器单元的第二位线 电压电平。 本文还提供了相关方法和系统。

公开(公告)号：US20070140015A1

公开(公告)日：2007-06-21

申请号：US11639807

申请日：2006-12-16

申请人： Shoichi Kawamura

发明人： Shoichi Kawamura

IPC分类号： G11C11/34

CPC分类号： G11C16/344 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/345

摘要： A nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device includes a memory cell formed in a first well outputs a first voltage in response to a reference voltage necessary for program and erase verify operations. A reference cell formed in a second well generates a second voltage in response to the reference voltage in the program and erase verify operations. A comparator circuit compares the first voltage to the second voltage to detect whether the verify operation for the memory cell has passed, in the verify operation. A bias applying unit applies the same bias voltage to the first and second wells in the verify operation: Although there is an over-erased cell, an erase verify, operation can be correctly performed.

摘要翻译： 非易失性半导体存储器件。 非易失性半导体存储器件包括形成在第一阱中的存储单元响应于编程和擦除验证操作所需的参考电压而输出第一电压。 形成在第二阱中的参考单元响应于程序中的参考电压和擦除验证操作而产生第二电压。 在验证操作中，比较器电路将第一电压与第二电压进行比较，以检测存储单元的验证操作是否已经过去。 偏置施加单元在验证操作中向第一和第二阱施加相同的偏置电压：尽管存在过擦除的单元，但可以正确地执行擦除验证操作。

公开(公告)号：US06614686B1

公开(公告)日：2003-09-02

申请号：US10069124

申请日：2002-03-01

申请人： Shoichi Kawamura

发明人： Shoichi Kawamura

IPC分类号： G11C1604

CPC分类号： G11C16/26 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491

摘要： The present invention provides a multi-bits non-volatile memory circuit having a cell transistor with non-conductive trap gate which has a cell array capable of reading a plural data simultaneously. The present invention is a non-volatile memory circuit in which a plurality of cell transistors M having a non-conductive trapping gate TG are arranged, comprising: a plurality of source-drain lines SDL, which are connected commonly with the source-drain regions SD1, SD2 of cell transistors adjacent in row direction, wherein these adjacent source-drain lines are set to a floating state F, a read-out voltage application state BL, a reference voltage state OV, a read-out voltage state BL, and a floating state F, and the source-drain lines SDL in the read-out voltage state is caused to function as bit lines, such that a plurality of data are read out simultaneously. The above states are generated by the page buffer P/B connected to the source-drain line. The data read and hold are performed by the page buffer.

摘要翻译： 本发明提供一种多位非易失性存储器电路，其具有具有非导电陷阱栅极的单元晶体管，其具有能够同时读取多个数据的单元阵列。 本发明是一种非易失性存储器电路，其中布置有具有非导电捕获栅极TG的多个单元晶体管M，包括：多个源极 - 漏极线SDL，其与源极 - 漏极区域共同连接 SD1，SD2，其中这些相邻的源极 - 漏极线被设置为浮置状态F，读出电压施加状态BL，基准电压状态OV，读出电压状态BL和 使浮置状态F和读出电压状态下的源极 - 漏极线SDL用作位线，使得同时读出多个数据。 上述状态由连接到源极 - 漏极线的页面缓冲器P / B产生。 数据读取和保持由页面缓冲区执行。

公开(公告)号：US06288940B1

公开(公告)日：2001-09-11

申请号：US09599462

申请日：2000-06-22

申请人： Shoichi Kawamura

发明人： Shoichi Kawamura

IPC分类号： G11C1600

CPC分类号： G11C29/76

摘要： A non-volatile semiconductor memory device comprises a plurality of memory cell units each of which includes a plurality of non-volatile memory cells capable of having data electrically rewritten; a storage unit; and an access inhibiting circuit. The storage unit stores therein the defect information of the memory cell unit not normally operating. The access inhibiting circuit judges the condition of the memory cell unit within the device according to the defect information stored in the storage unit. Access to the memory cell unit not normally operating is inhibited in accordance with the result of the judgement. Since the device can control the information of the memory cell unit not normally operating by itself, users of the device need not manage the defective memory cell unit. Consequently, the usability of the device is enhanced and the cost of a system mounting the device is curtailed. Particularly, it is effective for the non-volatile semiconductor memory device for file allowing the presence of inoperative memory cells.

摘要翻译： 非挥发性半导体存储器件包括多个存储单元单元，每个存储单元单元包括能够进行电气重写的数据的多个非易失性存储单元; 存储单元; 和访问禁止电路。 存储单元存储不正常操作的存储单元单元的缺陷信息。 访问禁止电路根据存储在存储单元中的缺陷信息来判断设备内的存储单元单元的状态。 根据判断结果禁止对正常工作的存储单元单元的访问。 由于设备可以控制自身不正常操作的存储单元单元的信息，所以设备的用户不需要管理有缺陷的存储单元单元。 因此，增强了设备的可用性，并且减少了安装设备的系统的成本。 特别地，非易失性半导体存储器件对于允许存在非操作存储单元的文件是有效的。

公开(公告)号：US06266275B1

公开(公告)日：2001-07-24

申请号：US09410512

申请日：1999-09-30

申请人： Paul-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

发明人： Paul-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C700

CPC分类号： G11C16/0483

摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。