公开(公告)号：US20230333861A1

公开(公告)日：2023-10-19

申请号：US18191074

申请日：2023-03-28

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Paul Walmsley ,  John Ingalls

IPC: G06F9/445

CPC classification number: G06F9/44505

Abstract: A first operating system process may be identified. The first operating system process may have instructions configured to be executed by a processor core. A first set of parameters may be determined based on an attribute of the first operating system process. For example, the first set of parameters may be determined based on an address space identifier, an address space stored in a page table base register, a virtual machine identifier, or a combination thereof. A component of the processor core may be configured using the first set of parameters. For example, one or more components, such as a branch predictor, a prefetcher, a dispatch unit, a vector unit, a clock controller, and the like, may be configured using the first set of parameters.

公开(公告)号：US20230153203A1

公开(公告)日：2023-05-18

申请号：US18097252

申请日：2023-01-15

Applicant: SiFive, Inc.

Inventor： Murali Vijayaraghavan ,  Krste Asanovic

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F9/30 ,  G06F12/1027 ,  G06F9/32

CPC classification number: G06F11/1068 ,  G06F9/321 ,  G06F9/30047 ,  G06F11/0772 ,  G06F11/3024 ,  G06F11/3037 ,  G06F12/1027

Abstract: Systems and methods are disclosed for checker cores for fault tolerant processing. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions of an instruction set; an outer memory system configured to store instructions and data; and a checker core configured to receive committed instruction packets from the processor core and check the committed instruction packets for errors, wherein the checker core is configured to utilize a memory pathway of the processor core to access the outer memory system by receiving instructions and data read from the outer memory system as portions of committed instruction packets from the processor core. For example, data flow from the processor core to the checker core may be limited to committed instruction packets received via dedicated a wire bundle.

公开(公告)号：US11429392B2

公开(公告)日：2022-08-30

申请号：US16362121

申请日：2019-03-22

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems and methods are disclosed for secure predictors for speculative execution. Some implementations may eliminate or mitigate side-channel attacks, such as the Spectre-class of attacks, in a processor. For example, an integrated circuit (e.g., a processor) for executing instructions includes a predictor circuit that, when operating in a first mode, uses data stored in a set of predictor entries to generate predictions. For example, the integrated circuit may be configured to: detect a security domain transition for software being executed by the integrated circuit; responsive to the security domain transition, change a mode of the predictor circuit from the first mode to a second mode and invoke a reset of the set of predictor entries, wherein the second mode prevents the use of a first subset of the predictor entries of the set of predictor entries; and, after completion of the reset, change the mode back to the first mode.

公开(公告)号：US20220236993A1

公开(公告)日：2022-07-28

申请号：US17718258

申请日：2022-04-11

Applicant: SiFive, Inc.

Inventor： Joshua Smith ,  Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.

公开(公告)号：US20210255859A1

公开(公告)日：2021-08-19

申请号：US17306373

申请日：2021-05-03

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.

公开(公告)号：US20200183687A1

公开(公告)日：2020-06-11

申请号：US16215328

申请日：2018-12-10

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.

公开(公告)号：US12253959B2

公开(公告)日：2025-03-18

申请号：US18024208

申请日：2021-09-01

Applicant: SiFive, Inc.

Inventor： Andrew Waterman ,  Krste Asanovic

IPC: G06F12/14 ,  G06F9/30

Abstract: Systems and methods are disclosed for memory protection for memory protection for gather-scatter operations. For example, an integrated circuit may include a processor core; a memory protection circuit configured to check for memory protection violations with a protection granule; and an index range circuit configured to: memoize a maximum value and a minimum value of a tuple of indices stored in a vector register of the processor core as the tuple of indices is written to the vector register; determine a range of addresses for a gather-scatter memory instruction that takes the vector register as a set of indices based on a base address of a vector in memory, the memoized minimum value, and the memoized maximum value; and check, using the memory protection circuit during a single clock cycle, whether accessing elements of the vector within the range of addresses will cause a memory protection violation.

公开(公告)号：US20240289495A1

公开(公告)日：2024-08-29

申请号：US18115457

申请日：2023-02-28

Applicant: SiFive, Inc.

Inventor： Krste Asanovic

IPC: G06F12/14

CPC classification number: G06F21/72

Abstract: Systems and methods are disclosed for address range encoding in a system on a chip with a securely partitioned memory space. For example, methods may include receiving, via a bus from a processor core, a memory request for a memory mapped resource; comparing an address included in the memory request to an address range, determined based on an address field and an address range configuration field, for a resource; comparing a first hardware security identifier from the memory request to a hardware security list associated with the resource when the address of the memory request is within the address range for the resource; and, based on the comparison of the first hardware security identifier with the hardware security list, determining whether to allow or reject access to the resource for the memory request.

公开(公告)号：US20240264839A1

公开(公告)日：2024-08-08

申请号：US18428319

申请日：2024-01-31

Applicant: SiFive, Inc.

Inventor： Andrew Waterman ,  Krste Asanovic ,  Josh Smith

IPC: G06F9/38 ,  G06F9/24

CPC classification number: G06F9/3806 ,  G06F9/24

Abstract: Systems and methods are disclosed for macro-op fusion in pipelined architectures. For example, some methods include detecting a sequence of macro-ops stored in an instruction decode buffer, the sequence of macro-ops including a first macro-op, followed by one or more intervening macro-ops, followed by a last macro-op; determining a micro-op that is equivalent to the first macro-op combined with the last macro-op; and forwarding the micro-op to one or more execution resource circuitries for execution.

公开(公告)号：US20240020126A1

公开(公告)日：2024-01-18

申请号：US18344986

申请日：2023-06-30

Applicant: SiFive, Inc.

Inventor： Andrew Waterman ,  Krste Asanovic

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30098

Abstract: Systems and methods are disclosed for fusion with destructive instructions. For example, an integrated circuit (e.g., a processor) for executing instructions includes a fusion circuitry that is configured to detect a sequence of macro-ops stored in a processor pipeline of the processor core, the sequence of macro-ops including a first macro-op identifying a first register as a destination register followed by a second macro-op identifying the first register as both a source register and as a destination register, wherein one or more intervening macro-ops occur between the first macro-op and the second macro-op in the program order; determine a micro-op that is equivalent to the first macro-op followed by the second macro-op; and forward the micro-op to at least one of the one or more execution resource circuitries for execution. For example, the sequence of macro-ops may be detected in a vector dispatch stage of a processor pipeline.