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21.发明授权公开(公告)号：US11630601B2
公开(公告)日：2023-04-18
申请号：US17515570
申请日：2021-11-01
Applicant: Silicon Motion, Inc.
Inventor： Cheng Yi , Kaihong Wang , Sheng-I Hsu , I-Ling Tseng
IPC: G06F3/06
Abstract: A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.
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22.发明申请公开(公告)号：US20220283732A1
公开(公告)日：2022-09-08
申请号：US17515570
申请日：2021-11-01
Applicant: Silicon Motion, Inc.
Inventor： Cheng Yi , Kaihong Wang , Sheng-I Hsu , I-Ling Tseng
IPC: G06F3/06
Abstract: A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.
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23.发明申请公开(公告)号：US20200371817A1
公开(公告)日：2020-11-26
申请号：US16732338
申请日：2020-01-01
Applicant: Silicon Motion, Inc.
Inventor： Sheng-I Hsu
Abstract: A method for performing dynamic throttling control with aid of configuration setting and associated apparatus such as a host device, a data storage device and a controller thereof are provided. The method includes: utilizing the host device to provide a user interface, to allow a user to select any of a plurality of throttling control configurations of the data storage device; and in response to the selection of said any of the plurality of throttling control configurations by the user, utilizing the host device to send throttling control information corresponding to said any of the plurality of throttling control configurations toward the data storage device, to perform the dynamic throttling control on the data storage device during programming the NV memory, for limiting power consumption of the data storage device during programming the NV memory, wherein the throttling control information indicates performing the dynamic throttling control is required.
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24.发明授权公开(公告)号：US10574271B2
公开(公告)日：2020-02-25
申请号：US16053815
申请日：2018-08-03
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Sheng-I Hsu
Abstract: A data storage system includes a processing circuit, a lookup table (LUT), and a decoding circuit. The processing circuit is arranged to receive a first logical block address (LBA) from a host. The LUT is arranged to store a storage address mapping to the first LBA. The decoding circuit is arranged to utilize the storage address to read storage data from a storing circuit, and decode a first data sector in the storage data according to an error checking and correcting code in the storage data, and the first data sector at least comprises a second LBA.
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公开(公告)号：US20200007168A1
公开(公告)日：2020-01-02
申请号：US16568221
申请日：2019-09-11
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Sheng-I Hsu
Abstract: A data storage system includes a processing circuit, a calculating circuit and an encoding circuit. The processing circuit receives a data byte from a host. The calculating circuit generates a cyclic redundancy check code according to an LBA, and combines the cyclic redundancy check code and the data byte into a data sector so that the data sector includes LBA-related information. The encoding circuit encodes the data sector to generate an error checking and correcting code, and combines the data sector and the error checking and correcting code into a storage data, so that the storage data includes the LBA-related information without including the LBA. Via the data sector and the storage data, the data storage system performs cyclic redundancy checking as well as error checking and correcting without storing the LBA for reducing 1-bit errors; and the LBA-related information does not include part or all of the LBA.
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Patent Agency Ranking
公开(公告)号：US20170075755A1
公开(公告)日：2017-03-16
申请号：US15260330
申请日：2016-09-09
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Sheng-I Hsu
CPC classification number: H03M13/2906 , G06F11/1012 , G06F12/0246 , G06F2212/1032 , G06F2212/214 , G06F2212/403 , G06F2212/7201 , H03M13/09 , H03M13/13
Abstract: A data storage system includes: a processing circuit arranged to receive a data bytes from a host; a calculating circuit arranged to generate a cyclic redundancy check code according to a logical block address, and combine the cyclic redundancy check code and the data bytes to be a data sector; and an encoding circuit arranged to encode the data sector to generate an error checking and correcting code, and combine the data sector and the error checking and correcting code to be a storing data.
Abstract translation: 数据存储系统包括：处理电路，被布置成从主机接收数据字节; 计算电路，被配置为根据逻辑块地址生成循环冗余校验码，并将所述循环冗余校验码与所述数据字节组合为数据扇区; 以及编码电路，被配置为对数据扇区进行编码以产生错误校验和校正码，并将数据扇区和错误校验和校正码组合成存储数据。
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27.发明申请公开(公告)号：US20150058700A1
公开(公告)日：2015-02-26
申请号：US14331591
申请日：2014-07-15
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Yang-Chih Shen , Sheng-I Hsu
IPC: G06F11/10
CPC classification number: G06F11/108 , G06F11/1012 , G06F2211/109
Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After all messages within a RAID (Redundant Array of Independent Disk) group are programmed, it is determined whether a vertical ECC (Error Correction Code) within the RAID group has been generated. The processing unit directs a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical ECC to be programmed to the storage unit.
Abstract translation: 用于访问由处理单元执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 在RAID（独立磁盘冗余阵列）组中的所有消息被编程之后，确定是否已经生成RAID组内的垂直ECC（纠错码）。 处理单元引导DMA（直接存储器访问）控制器从DRAM（动态随机存取存储器）获得垂直ECC，并且当生成RAID组内的垂直ECC时，将垂直ECC存储到缓冲器，从而使垂直 ECC被编程到存储单元。
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公开(公告)号：US20250055463A1
公开(公告)日：2025-02-13
申请号：US18928216
申请日：2024-10-28
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
IPC: H03K21/02 , G06F1/3234 , H03K5/00 , H03K21/10 , H03K21/40
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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公开(公告)号：US11748022B2
公开(公告)日：2023-09-05
申请号：US17519685
申请日：2021-11-05
Applicant: Silicon Motion, Inc.
Inventor： Sheng-I Hsu
IPC: G06F3/06
CPC classification number: G06F3/0653 , G06F3/0604 , G06F3/068 , G06F3/0656 , G06F3/0679 , G06F3/0683
Abstract: The invention introduces an apparatus for controlling different types of storage units, at least including: an interface and a processing unit. The interface connects at least two types of storage units, which include at least a nonvolatile hybrid memory. The processing unit is configured to operably access data to the different types of storage units through the interface.
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公开(公告)号：US11705907B2
公开(公告)日：2023-07-18
申请号：US17707992
申请日：2022-03-30
Applicant: Silicon Motion, Inc.
Inventor： Tien-Hsing Yao , Chun-Cheng Lee , Sheng-I Hsu
CPC classification number: H03K21/026 , G06F1/3275 , H03K5/00006 , H03K21/10 , H03K21/406
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
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