公开(公告)号：US20170125429A1

公开(公告)日：2017-05-04

申请号：US15295022

申请日：2016-10-17

Applicant: Silicon Storage Technology, Inc.

Inventor： CHIEN-SHENG SU ,  FENG ZHOU ,  JENG-WEI YANG ,  HIEU VAN TRAN ,  NHAN DO

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.