公开(公告)号：US20170125429A1

公开(公告)日：2017-05-04

申请号：US15295022

申请日：2016-10-17

Applicant: Silicon Storage Technology, Inc.

Inventor： CHIEN-SHENG SU ,  FENG ZHOU ,  JENG-WEI YANG ,  HIEU VAN TRAN ,  NHAN DO

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

公开(公告)号：US20170098654A1

公开(公告)日：2017-04-06

申请号：US15225393

申请日：2016-08-01

Applicant: Silicon Storage Technology, Inc.

Inventor： FENG ZHOU ,  XIAN LIU ,  JENG-WEI YANG ,  CHIEN-SHENG SU ,  NHAN DO

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/49

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/8238 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.

公开(公告)号：US20150270372A1

公开(公告)日：2015-09-24

申请号：US14733904

申请日：2015-06-08

Applicant: Silicon Storage Technology, Inc.

Inventor： CHIEN-SHENG SU ,  MANDANA TADAYONI ,  YUEH-HSIN CHEN

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66492 ,  H01L21/265 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7833

Abstract: A transistor and method of making same include a substrate, a conductive gate over the substrate and a channel region in the substrate under the conductive gate. First and second insulating spacers are laterally adjacent to first and second sides of the conductive gate. A source region in the substrate is adjacent to but laterally spaced from the first side of the conductive gate and the first spacer, and a drain region in the substrate is adjacent to but laterally spaced apart from the second side of the conductive gate and the second spacer. First and second LD regions are in the substrate and laterally extend between the channel region and the source or drain regions respectively, each with a portion thereof not disposed under the first and second spacers nor under the conductive gate, and each with a dopant concentration less than that of the source or drain regions.

Abstract translation: 晶体管及其制造方法包括衬底，衬底上的导电栅极和导电栅极下的衬底中的沟道区。 第一和第二绝缘间隔件横向邻近导电栅极的第一和第二侧。 衬底中的源极区域与导电栅极和第一间隔物的第一侧相邻但是横向间隔开，并且衬底中的漏极区域与导电栅极的第二侧相邻但横向间隔开，并且第二 间隔 第一LD区域和第二LD区域分别位于衬底中并分别在沟道区域和源极或漏极区域之间横向延伸，每个区域的一部分没有设置在第一和第二间隔物之下，也不设置在导电栅极之下，并且每个具有掺杂剂浓度 比源区或漏区。

公开(公告)号：US20230238453A1

公开(公告)日：2023-07-27

申请号：US18126954

申请日：2023-03-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  XIAN LIU ,  CHIEN-SHENG SU ,  Nhan DO ,  CHUNMING WANG

IPC: H01L29/66 ,  H01L29/788 ,  H01L27/07 ,  H01L29/08 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L29/788 ,  H01L27/0705 ,  H01L29/0847 ,  H01L29/40114 ,  H01L28/00 ,  H01L29/42328 ,  H01L29/66545 ,  G11C2216/10 ,  H01L29/6653

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US20170103991A1

公开(公告)日：2017-04-13

申请号：US15264457

申请日：2016-09-13

Applicant: Silicon Storage Technology, Inc.

Inventor： JINHO KIM ,  CHIEN-SHENG SU ,  FENG ZHOU ,  XIAN LIU ,  NHAN DO ,  PRATEEP TUNTASOOD ,  PARVIZ GHAZAVI

IPC: H01L27/115

CPC classification number: H01L27/11531 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.