公开(公告)号：US20230387116A1

公开(公告)日：2023-11-30

申请号：US18450146

申请日：2023-08-15

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/118 ,  H01L21/84 ,  H01L27/12 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/11807 ,  H01L21/845 ,  H01L27/1211 ,  H01L23/528 ,  H01L2924/0002

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

公开(公告)号：US20230275160A1

公开(公告)日：2023-08-31

申请号：US18315317

申请日：2023-05-10

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L29/786 ,  H01L27/092 ,  B82Y10/00 ,  H01L27/02 ,  H01L29/06 ,  H01L27/118 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L27/092 ,  B82Y10/00 ,  H01L27/0207 ,  H01L29/0673 ,  H01L27/11807 ,  H01L29/42392 ,  H01L21/823871

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

公开(公告)号：US20220246769A1

公开(公告)日：2022-08-04

申请号：US17724143

申请日：2022-04-19

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/06 ,  H01L29/775 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

公开(公告)号：US20220173254A1

公开(公告)日：2022-06-02

申请号：US17674568

申请日：2022-02-17

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L29/786 ,  H01L27/092 ,  B82Y10/00 ,  H01L27/02 ,  H01L29/06 ,  H01L27/118 ,  H01L29/423

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

公开(公告)号：US20190237465A1

公开(公告)日：2019-08-01

申请号：US16383044

申请日：2019-04-12

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/088 ,  H01L29/66 ,  H03K19/00 ,  H01L21/8234

Abstract: Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first n-channel transistor is comprised of n fin transistor(s) having an identical gate length and an identical gate width where n is equal to or greater than one, and has its gate connected to a first input node. The second n-channel transistor is comprised of m fin transistors having the same gate length and the same gate width where m is greater than n, and has its gate connected to a second input node.

公开(公告)号：US20190164950A1

公开(公告)日：2019-05-30

申请号：US16264046

申请日：2019-01-31

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/02 ,  H01L29/66 ,  H01L23/528

CPC classification number: H01L27/0207 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.

公开(公告)号：US20190109133A1

公开(公告)日：2019-04-11

申请号：US16211919

申请日：2018-12-06

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/088 ,  H01L21/84 ,  H01L27/118 ,  H01L27/12 ,  H01L23/528 ,  H01L27/02 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

公开(公告)号：US20190074297A1

公开(公告)日：2019-03-07

申请号：US16182342

申请日：2018-11-06

Applicant: SOCIONEXT INC.

Inventor： Keisuke KISHISHITA ,  Hiroyuki SHIMBO

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L23/482 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Provided is a layout configuration that helps facilitate manufacturing a semiconductor integrated circuit device including a nanowire FET. A nanowire FET in a standard cell includes Na (where Na is an integer of 2 or more) nanowires extending in an X direction, and a nanowire FET in a standard cell includes Nb (where Nb is an integer of 1 or more and less than Na) nanowires extending in the X direction. At least one of both ends, in the Y direction, of a pad of the nanowire FET is aligned in the X direction with an associated one of both ends, in the Y direction, of a pad of the nanowire FET.

公开(公告)号：US20220392921A1

公开(公告)日：2022-12-08

申请号：US17887913

申请日：2022-08-15

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/118 ,  H01L29/06 ,  H01L27/092 ,  H01L27/02

Abstract: Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.

公开(公告)号：US20220278096A1

公开(公告)日：2022-09-01

申请号：US17744141

申请日：2022-05-13

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/118 ,  H01L21/84 ,  H01L27/12 ,  H01L23/528

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.