公开(公告)号：US06675248B1

公开(公告)日：2004-01-06

申请号：US09678034

申请日：2000-10-03

Applicant: Sompong Paul Olarig ,  Usha Rajagopalan ,  Ronald Timothy Horan

Inventor： Sompong Paul Olarig ,  Usha Rajagopalan ,  Ronald Timothy Horan

IPC: G06F1314

CPC classification number: G06F13/385

Abstract: A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth. Alternate embodiments of the AGP to AGP Bridge can accommodate the single 64-bit AGP bus for increased performance. Another alternate embodiment can accommodate peer-to-peer transfer of data between AGP busses on the bridge.

Abstract translation: 具有至少一个中央处理单元，系统存储器和能够接受AGP总线的核心逻辑的计算机系统具有AGP连接到标准AGP总线的AGP桥。 AGP到AGP桥可以容纳两个或更多AGP兼容的设备，可以通过AGP到AGP桥通过标准AGP总线访问。 在AGP到AGP桥接器之间还提供PCI到存储器桥，使得PCI设备可以连接到AGP到AGP桥。 AGP到AGP桥配有一个总体流量控制逻辑，用于控制数据传输到或来自各种AGP设备和连接到计算机系统的核心逻辑的标准AGP总线。 AGP到AGP Bridge可以使用标准的32位AGP总线以及（两个）双32位总线来增强带宽。 在本发明的替代实施例中，双32位总线可以组合以形成单个64位总线，以增加可用带宽。 AGP到AGP Bridge的替代实施例可以容纳单个64位AGP总线，以提高性能。 另一替代实施例可以适应桥上AGP总线之间的数据对等传输。

公开(公告)号：US06639794B2

公开(公告)日：2003-10-28

申请号：US10024165

申请日：2001-12-18

Applicant: Sompong Paul Olarig ,  Donald Joseph Stoddard ,  Michael Hansen

Inventor： Sompong Paul Olarig ,  Donald Joseph Stoddard ,  Michael Hansen

IPC: H05K720

CPC classification number: H05K7/207 ,  H05K7/20581

Abstract: A chassis with an adaptive fan control is provided for electronic equipment. The adaptive fan control is responsive to at least one condition within one or more airflow sections within the chassis and may increase or decrease airflow in response to the condition.

Abstract translation: 为电子设备提供了具有自适应风扇控制的机箱。 自适应风扇控制响应于底盘内的一个或多个气流部分内的至少一个状态，并可响应于该状况而增加或减少气流。

公开(公告)号：US06567880B1

公开(公告)日：2003-05-20

申请号：US10109441

申请日：2002-03-28

Applicant: Sompong Paul Olarig

Inventor： Sompong Paul Olarig

IPC: G06F1300

CPC classification number: G06F13/4027 ,  G06F3/14 ,  G06F13/405

Abstract: A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port (“AGP”) bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect (“PCI”) device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.

Abstract translation: 在计算机系统中提供核心逻辑芯片组以提供主机和存储器总线之间的桥接，以及适用于两个AGP设备的操作的加速图形端口（“AGP”）总线，或者一个AGP设备和一个外围组件互连（“ PCI“）设备。 具有用于PCI和AGP接口信号的规定的公共AGP总线连接到核心逻辑芯片组和AGP和/或PCI设备。 核心逻辑芯片组具有对连接到AGP总线的每个AGP和/或PCI设备具有请求（“REQ”）和Grant（“GNT”）信号线的AGP / PCI仲裁器。 另一个实施例具有用于多个AGP设备的多个AGP总线。 这允许并发操作连接到不同AGP总线的AGP设备。 两个AGP总线可以组合连接到一个64位PCI设备。

公开(公告)号：US06260127B1

公开(公告)日：2001-07-10

申请号：US09114426

申请日：1998-07-13

Applicant: Sompong Paul Olarig ,  David J. Koenen ,  Chai S. Heng

Inventor： Sompong Paul Olarig ,  David J. Koenen ,  Chai S. Heng

IPC: G06F1300

CPC classification number: G06F13/1694

Abstract: A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module. Typically, between the tiers a protocol is used which is representative of a typical clocked synchronous dynamic random access memory (SDRAM), although another protocol could be used. From the perspective of the processor bus or host bus coupled to the front end of the first memory controller, the entire memory controller system behaves as a single memory controller. From the perspective of memory, the back end of the RAM personality module is seen as a memory controller designed specifically to be configured for that memory type. Consequently, although the front end of the RAM personality module can be standardized across the system, compatible with the back end of the first memory controller, and in most embodiments of the present invention, the back end of the RAM personality module differs among the controller modules in the second tier, according to the variety of the memory modules in the memory system.

公开(公告)号：US06249830B1

公开(公告)日：2001-06-19

申请号：US09532109

申请日：2000-03-21

Applicant: Dale J. Mayer ,  Sompong Paul Olarig ,  William F. Whiteman ,  David F. Heinrich

Inventor： Dale J. Mayer ,  Sompong Paul Olarig ,  William F. Whiteman ,  David F. Heinrich

IPC: G06F1300

CPC classification number: G06F13/24

Abstract: A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which computer system includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.

Abstract translation: 一种用于在对称多处理系统中支持指定为总线代理的多个分布式中断控制器的方法，该方法包括以下步骤：为每个总线代理分配唯一的标识号，从四个数据线上接收来自总线代理的总线请求， 四，并向所选择的一个请求巴士代理人授予公共汽车所有权。 类似地，一种计算机系统，其支持在对称多处理系统中指定为总线代理的多个分布式中断控制器，该计算机系统包括用于向每个总线代理分配唯一标识号的结构，用于从总线代理接收总线请求的四个数据线 以四组为单位，以及将公交车所有权授予选定的一个请求巴士代理人的结构。

公开(公告)号：US5937173A

公开(公告)日：1999-08-10

申请号：US873420

申请日：1997-06-12

Applicant: Sompong Paul Olarig ,  Dwight D. Riley ,  Ronald Timothy Horan

Inventor： Sompong Paul Olarig ,  Dwight D. Riley ,  Ronald Timothy Horan

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4027

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect ("RegPCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.

Abstract translation: 在可以被配置为加速图形端口（“AGP”）总线与主机与存储器总线之间的桥接的计算机系统中提供了多用途核心逻辑芯片组，作为附加的注册的外围组件互连（“ RegPCI“）总线和主机和内存总线，或作为主PCI总线和附加RegPCI总线之间的桥梁。 多用途芯片组的功能是在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的注册PCI总线桥接器。 多用核心逻辑芯片组具有仲裁器，其具有针对在附加的已注册PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线。 可以通过硬件信号输入或在计算机系统配置或上电自检（“POST”）期间通过软件来选择多用途核心逻辑芯片组中的总线桥（AGP或RegPCI）的类型。 也可以在检测到连接到公共AGP / RegPCI总线的AGP或RegPCI设备时确定软件配置。

公开(公告)号：US5881293A

公开(公告)日：1999-03-09

申请号：US699921

申请日：1996-08-20

Applicant: Sompong Paul Olarig ,  Dale J. Mayer ,  William F. Whiteman

Inventor： Sompong Paul Olarig ,  Dale J. Mayer ,  William F. Whiteman

IPC: G06F15/16 ,  G06F9/46 ,  G06F13/24 ,  G06F15/177 ,  G06F13/00

CPC classification number: G06F13/24

Abstract: A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

Abstract translation: 一种用于多处理器环境的分布式中断控制器系统，具有经由专用总线耦合至少一个中央可编程中断控制器（COPIC）的至少两个本地可编程中断控制器（LOPIC）。 至少一个COPIC中的一个用作主仲裁器，而每个可与其对应处理单元集成的LOPIC和其他非主控COPIC被视为总线代理。 总线授权是通过“循环”仲裁协议实现的。 对于中断的分布式发送，主仲裁器将与每个总线代理相关联的当前任务优先级寄存器值进行比较，以确定最不忙于传递中断的代理。

公开(公告)号：US5867645A

公开(公告)日：1999-02-02

申请号：US723767

申请日：1996-09-30

Applicant: Sompong Paul Olarig

Inventor： Sompong Paul Olarig

IPC: G06F13/00 ,  G06F11/20 ,  G06F11/00

CPC classification number: G06F11/2007 ,  G06F2201/85

Abstract: A computer system having an interconnection apparatus for interconnecting processors, peripherals, and memories, including a bus structure with an extended-bus portion and a non-extended-bus portion, and the extended-bus-compliant devices having a status register. The extended-bus-compliant devices are operable in either extended-bus mode involving both the extended-bus portion and non-extended-bus portion of the bus structure, or non-extended-bus mode involving only the non-extended-bus portion. Upon detecting a transmission error or device-related fault, the contents of the status register are altered so as to render the extended-bus-compliant devices operable in the non-extended-bus mode using only the non-extended-bus portion.

Abstract translation: 具有用于互连处理器，外围设备和存储器的互连装置的计算机系统，包括具有扩展总线部分的总线结构和非扩展总线部分，以及具有状态寄存器的扩展总线兼容装置。 扩展总线兼容设备可以以涉及总线结构的扩展总线部分和非扩展总线部分的扩展总线模式操作，或者仅涉及非扩展总线部分的非扩展总线模式 。 在检测到传输错误或与设备有关的故障时，状态寄存器的内容被改变，以便仅使用非扩展总线部分使得扩展总线兼容的设备在非扩展总线模式下可操作。

公开(公告)号：US5857086A

公开(公告)日：1999-01-05

申请号：US855401

申请日：1997-05-13

Applicant: Ronald Timothy Horan ,  Sompong Paul Olarig

Inventor： Ronald Timothy Horan ,  Sompong Paul Olarig

IPC: G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/385 ,  G06F13/4027

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 32 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 32 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 32 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of a PCI device connected to the common bus.

Abstract translation: 在可以被配置为加速图形端口（“AGP”）总线与主机和存储器总线之间的桥的计算机系统中提供了多用途核心逻辑芯片组，作为32位附加外围组件互连 “PCI”）总线和主机和存储器总线，或作为主PCI总线和附加PCI总线之间的桥梁。 多用芯片组的功能是在计算机系统制造时或在现场确定是否实现AGP总线桥接器或额外的32位PCI总线桥接器的功能。 多用核心逻辑芯片组具有对在附加32位PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线的仲裁器。 可以通过硬件信号输入，计算机系统配置或上电自检（“POST”）期间的软件来选择多用途核心逻辑芯片组中的总线桥（AGP或PCI）类型。 在检测到连接到公共总线的PCI设备时也可以确定软件配置。

公开(公告)号：US09330282B2

公开(公告)日：2016-05-03

申请号：US12481806

申请日：2009-06-10

Applicant: Marius Strom ,  Sompong Paul Olarig ,  Chris Lionetti

Inventor： Marius Strom ,  Sompong Paul Olarig ,  Chris Lionetti

IPC: G06F11/30 ,  G06F21/80 ,  G06F21/79

CPC classification number: G06F21/80 ,  G06F21/79 ,  G06F2221/2143

Abstract: A card can be communicationally coupled to a storage device. The card can then cause the storage device to perform stand-alone tasks without a computing device. The card can invoke instructions already present in the firmware of the storage device or the card can first copy instructions to the firmware and then invoke them. The card can cause the storage device to perform actions, such as a secure erase, and the storage device can remain inaccessible until such actions are performed, even if power is interrupted. The card can also receive information from the storage devices and then use that information with a new storage device to, for example, enable the new storage device to take the place of, and reconstruct the data of, the old storage device in a storage array directly from other storage devices in the array and without burdening a computing device or array controller.

Abstract translation: 卡可以通信地耦合到存储设备。 然后，卡可以使存储设备在没有计算设备的情况下执行独立任务。 该卡可以调用已经存在于存储设备的固件中的指令，或者卡可以首先将指令复制到固件，然后调用它们。 该卡可以使存储设备执行诸如安全擦除的操作，并且即使电源中断，存储设备也可以保持不可访问，直到执行这些动作。 该卡还可以从存储设备接收信息，然后将该信息与新的存储设备一起使用，例如，使新的存储设备能够代替和重构存储阵列中的旧存储设备的数据 直接从阵列中的其他存储设备，并且不会使计算设备或阵列控制器负担。