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1.发明授权Dual purpose computer bridge interface for accelerated graphics port or registered peripheral component interconnect devices 失效用于加速图形端口或注册外设组件互连设备的双用途计算机网桥接口
公开(公告)号：US5937173A
公开(公告)日：1999-08-10
申请号：US873420
申请日：1997-06-12
CPC分类号： G06F13/4027
摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect ("RegPCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.
摘要翻译： 在可以被配置为加速图形端口（“AGP”）总线与主机与存储器总线之间的桥接的计算机系统中提供了多用途核心逻辑芯片组，作为附加的注册的外围组件互连（“ RegPCI“）总线和主机和内存总线，或作为主PCI总线和附加RegPCI总线之间的桥梁。 多用途芯片组的功能是在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的注册PCI总线桥接器。 多用核心逻辑芯片组具有仲裁器，其具有针对在附加的已注册PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线。 可以通过硬件信号输入或在计算机系统配置或上电自检（“POST”）期间通过软件来选择多用途核心逻辑芯片组中的总线桥（AGP或RegPCI）的类型。 也可以在检测到连接到公共AGP / RegPCI总线的AGP或RegPCI设备时确定软件配置。
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2.发明授权Apparatus method and system for 64 bit peripheral component interconnect bus using accelerated graphics port logic circuits 失效使用加速图形端口逻辑电路的64位外设组件互连总线的装置方法和系统
公开(公告)号：US5859989A
公开(公告)日：1999-01-12
申请号：US855341
申请日：1997-05-13
CPC分类号： G06T11/00
摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 64 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 64 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 64 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of a PCI device connected to the common bus.
摘要翻译： 在可以配置为加速图形端口（“AGP”）总线和主机与存储器总线之间的桥接器的计算机系统中提供了多用途核心逻辑芯片组，作为64位附加外围组件互连 “PCI”）总线和主机和存储器总线，或作为主PCI总线和附加PCI总线之间的桥梁。 多个使用芯片组的功能在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的64位PCI总线桥接器。 多用核心逻辑芯片组具有对在额外的64位PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线的仲裁器。 在多用途核心逻辑芯片组中选择总线桥（AGP或PCI）的类型可以通过硬件信号输入，或者在计算机系统配置或上电自检（“POST”）期间由软件进行。 在检测到连接到公共总线的PCI设备时也可以确定软件配置。
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3.发明授权
公开(公告)号：US6167476A
公开(公告)日：2000-12-26
申请号：US160280
申请日：1998-09-24
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth. Alternate embodiments of the AGP to AGP Bridge can accommodate the single 64-bit AGP bus for increased performance. Another alternate embodiment can accommodate peer-to-peer transfer of data between AGP busses on the bridge.
摘要翻译： 具有至少一个中央处理单元，系统存储器和能够接受AGP总线的核心逻辑的计算机系统具有AGP连接到标准AGP总线的AGP桥。 AGP到AGP桥可以容纳两个或更多AGP兼容的设备，可以通过AGP到AGP桥通过标准AGP总线访问。 在AGP到AGP桥接器之间还提供PCI到存储器桥，使得PCI设备可以连接到AGP到AGP桥。 AGP到AGP桥配有一个总体流量控制逻辑，用于控制数据传输到或来自各种AGP设备和连接到计算机系统的核心逻辑的标准AGP总线。 AGP到AGP Bridge可以使用标准的32位AGP总线以及（两个）双32位总线来增强带宽。 在本发明的替代实施例中，双32位总线可以组合以形成单个64位总线，以增加可用带宽。 AGP到AGP Bridge的替代实施例可以容纳单个64位AGP总线，以提高性能。 另一替代实施例可以适应桥上AGP总线之间的数据对等传输。
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4.发明授权Dual purpose apparatus, method and system for accelerated graphics port and peripheral component interconnect 失效用于加速图形端口和外围组件互连的双重目的设备，方法和系统
公开(公告)号：US5889970A
公开(公告)日：1999-03-30
申请号：US853289
申请日：1997-05-09
CPC分类号： G06F3/14 , G06F12/0875 , G09G5/393 , G09G2360/121
摘要： A core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and either an AGP or PCI device(s). The core logic chip set also has an AGP/PCI arbiter having additional Request ("REQ") and Grant ("GNT") signal lines so that more than one PCI device may be utilized on the additional PCI bus. Selection of the type of bus bridge (AGP or PCI) in the core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or PCI device connected to the common bus.
摘要翻译： 在计算机系统中提供了一种核心逻辑芯片组，其可被配置为加速图形端口（“AGP”）总线与主机和存储器总线之间的桥接器，作为附加外围部件互连（“PCI”） 总线和主机和内存总线，或作为主PCI总线和附加PCI总线之间的桥梁。 具有PCI和AGP接口信号的公共总线连接到核心逻辑芯片组和AGP或PCI设备。 核心逻辑芯片组还具有具有附加请求（“REQ”）和Grant（“GNT”）信号线的AGP / PCI仲裁器，使得可以在附加PCI总线上使用多于一个PCI设备。 在核心逻辑芯片组中选择总线桥（AGP或PCI）的类型可以通过硬件信号输入，计算机系统配置或上电自检（“POST”）期间的软件进行。 也可以在检测到连接到公共总线的AGP或PCI设备时确定软件配置。
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5.发明授权公开(公告)号：US06675248B1
公开(公告)日：2004-01-06
申请号：US09678034
申请日：2000-10-03
IPC分类号： G06F1314
CPC分类号： G06F13/385
摘要： A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth. Alternate embodiments of the AGP to AGP Bridge can accommodate the single 64-bit AGP bus for increased performance. Another alternate embodiment can accommodate peer-to-peer transfer of data between AGP busses on the bridge.
摘要翻译： 具有至少一个中央处理单元，系统存储器和能够接受AGP总线的核心逻辑的计算机系统具有AGP连接到标准AGP总线的AGP桥。 AGP到AGP桥可以容纳两个或更多AGP兼容的设备，可以通过AGP到AGP桥通过标准AGP总线访问。 在AGP到AGP桥接器之间还提供PCI到存储器桥，使得PCI设备可以连接到AGP到AGP桥。 AGP到AGP桥配有一个总体流量控制逻辑，用于控制数据传输到或来自各种AGP设备和连接到计算机系统的核心逻辑的标准AGP总线。 AGP到AGP Bridge可以使用标准的32位AGP总线以及（两个）双32位总线来增强带宽。 在本发明的替代实施例中，双32位总线可以组合以形成单个64位总线，以增加可用带宽。 AGP到AGP Bridge的替代实施例可以容纳单个64位AGP总线，以提高性能。 另一替代实施例可以适应桥上AGP总线之间的数据对等传输。
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6.发明授权Apparatus method and system for peripheral component interconnect bus using accelerated graphics port logic circuits 失效使用加速图形端口逻辑电路的外围组件互连总线的装置方法和系统
公开(公告)号：US5857086A
公开(公告)日：1999-01-05
申请号：US855401
申请日：1997-05-13
CPC分类号： G06F13/385 , G06F13/4027
摘要： A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 32 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 32 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 32 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of a PCI device connected to the common bus.
摘要翻译： 在可以被配置为加速图形端口（“AGP”）总线与主机和存储器总线之间的桥的计算机系统中提供了多用途核心逻辑芯片组，作为32位附加外围组件互连 “PCI”）总线和主机和存储器总线，或作为主PCI总线和附加PCI总线之间的桥梁。 多用芯片组的功能是在计算机系统制造时或在现场确定是否实现AGP总线桥接器或额外的32位PCI总线桥接器的功能。 多用核心逻辑芯片组具有对在附加32位PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线的仲裁器。 可以通过硬件信号输入，计算机系统配置或上电自检（“POST”）期间的软件来选择多用途核心逻辑芯片组中的总线桥（AGP或PCI）类型。 在检测到连接到公共总线的PCI设备时也可以确定软件配置。
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公开(公告)号：US5892964A
公开(公告)日：1999-04-06
申请号：US885062
申请日：1997-06-30
CPC分类号： G06F13/4027 , G06F13/385
摘要： A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port ("AGP") bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect ("PCI") device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request ("REQ") and Grant ("GNT") signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.
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