公开(公告)号：US20220157391A1

公开(公告)日：2022-05-19

申请号：US17525712

申请日：2021-11-12

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Raul Adrian Cernea

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

Abstract: A method is for ensuring data integrity in memory pages includes: dividing the memory pages into a predetermined number of refresh groups; and for each write operation to be performed on a selected memory page: (a) selecting one of the refresh groups; (b) reading data from the memory pages of the selected refresh group; and (d) concurrently (i) performing the write operation on the selected memory page, and (ii) writing back the data read into the memory pages of the selected refresh group.

公开(公告)号：US10950616B2

公开(公告)日：2021-03-16

申请号：US16792808

申请日：2020-02-17

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Raul Adrian Cernea

IPC: H01L27/11 ,  G11C16/04 ,  H01L27/11578 ,  G11C7/18 ,  H03K19/20 ,  H03K19/1776 ,  G11C16/08 ,  G11C16/24 ,  H01L29/786

Abstract: A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

公开(公告)号：US10672484B2

公开(公告)日：2020-06-02

申请号：US16193292

申请日：2018-11-16

Applicant: Sunrise Memory Corporation

Inventor： Raul Adrian Cernea

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/24 ,  G11C16/32 ,  H01L27/11582 ,  G11C16/08 ,  G11C7/06 ,  G11C7/12

Abstract: Algorithms for fast data retrieval, low power consumption in a 3D or planar non-volatile array of memory cells, connected between an accessible drain string and a floating, not directly accessible, source string, in a NOR-logic type of architecture, are presented.

公开(公告)号：US10608008B2

公开(公告)日：2020-03-31

申请号：US16006612

申请日：2018-06-12

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Raul Adrian Cernea

IPC: G11C16/04 ,  H01L27/11578 ,  G11C7/18 ,  H03K19/20 ,  H03K19/1776 ,  G11C16/08 ,  G11C16/24 ,  H01L29/786

Abstract: A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

公开(公告)号：US20200051990A1

公开(公告)日：2020-02-13

申请号：US16509282

申请日：2019-07-11

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Raul Adrian Cernea ,  George Samachisa ,  Wu-Yi Henry Chien

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C11/56 ,  H01L27/06 ,  H01L27/12

Abstract: A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.