公开(公告)号：US20250113493A1

公开(公告)日：2025-04-03

申请号：US18919262

申请日：2024-10-17

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Christopher J. Petti ,  Vinod Purayath ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B51/30 ,  G11C11/22 ,  H10B51/20

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

公开(公告)号：US12160996B2

公开(公告)日：2024-12-03

申请号：US18483322

申请日：2023-10-09

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Christopher J. Petti ,  Vinod Purayath ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B51/30 ,  G11C11/22 ,  H10B51/20

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

公开(公告)号：US11839086B2

公开(公告)日：2023-12-05

申请号：US17812375

申请日：2022-07-13

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Christopher J. Petti ,  Vinod Purayath ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B51/30 ,  G11C11/22 ,  H10B51/20

CPC classification number: H10B51/30 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/2275 ,  H10B51/20

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

公开(公告)号：US12256547B2

公开(公告)日：2025-03-18

申请号：US17494549

申请日：2021-10-05

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Christopher J. Petti ,  George Samachisa ,  Wu-Yi Henry Chien

IPC: H10B43/35 ,  G11C16/04 ,  H10B43/20

Abstract: A thin-film storage transistor in a NOR memory string has a gate dielectric layer that includes a silicon oxide nitride (SiON) tunnel dielectric layer. In one embodiment, the SiON tunnel dielectric layer has a thickness between 0.5 to 5.0 nm thick and an index of refraction between 1.5 and 1.9. The SiON tunnel dielectric layer may be deposited at between 720° C. and 900° C. and between 100 and 800 mTorr vapor pressure, using an LPCVD technique under DCS, N2O, and NH3 gas flows. The SiON tunnel dielectric layer may have a nitrogen content of 1-30 atomic percent (at %).

公开(公告)号：US11515432B2

公开(公告)日：2022-11-29

申请号：US17155673

申请日：2021-01-22

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Sayeef Salahuddin ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L21/8239 ,  H01L29/792 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/423

Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

公开(公告)号：US11069696B2

公开(公告)日：2021-07-20

申请号：US16509282

申请日：2019-07-11

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Raul Adrian Cernea ,  George Samachisa ,  Wu-Yi Henry Chien

IPC: H01L27/112 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/12 ,  G11C11/56 ,  H01L27/06

Abstract: A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.

公开(公告)号：US10896916B2

公开(公告)日：2021-01-19

申请号：US16194225

申请日：2018-11-16

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  George Samachisa ,  Yupin Fong

IPC: H01L27/11582 ,  H01L29/49 ,  H01L29/423

Abstract: A non-volatile “reverse memory cell” suitable for use as a building block for a 3-dimensional memory array includes a charge-trapping layer which is programmed or charged through gate-injection, rather than channel-injection. Such a reverse cell may be implemented as either an n-channel memory cell or a p-channel memory cell, without incurring design or process penalties, or any complexity in programming or erase operations. Furthermore, all reading, programming, erase, program-inhibiting operations may be carried out in the reverse memory cell using only positive or only negative voltages, thereby simplifying both the design and the power management operations.

公开(公告)号：US20190157296A1

公开(公告)日：2019-05-23

申请号：US16194225

申请日：2018-11-16

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  George Samachisa ,  Yupin Fong

IPC: H01L27/11582 ,  H01L29/49 ,  H01L29/423

Abstract: A non-volatile “reverse memory cell” suitable for use as a building block for a 3-dimensional memory array includes a charge-trapping layer which is programmed or charged through gate-injection, rather than channel-injection. Such a reverse cell may be implemented as either an n-channel memory cell or a p-channel memory cell, without incurring design or process penalties, or any complexity in programming or erase operations. Furthermore, all reading, programming, erase, program-inhibiting operations may be carried out in the reverse memory cell using only positive or only negative voltages, thereby simplifying both the design and the power management operations.

公开(公告)号：US12183834B2

公开(公告)日：2024-12-31

申请号：US18046433

申请日：2022-10-13

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Sayeef Salahuddin ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H10B43/30

Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

公开(公告)号：US20240040798A1

公开(公告)日：2024-02-01

申请号：US18483322

申请日：2023-10-09

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Christopher J. Petti ,  Vinod Purayath ,  George Samachisa ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B51/30 ,  G11C11/22 ,  H10B51/20

CPC classification number: H10B51/30 ,  G11C11/2275 ,  G11C11/2273 ,  G11C11/223 ,  H10B51/20

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.