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    3-DIMENSIONAL NOR STRINGS WITH SEGMENTED SHARED SOURCE REGIONS
    4.
    发明申请
    3-DIMENSIONAL NOR STRINGS WITH SEGMENTED SHARED SOURCE REGIONS 有权

    公开(公告)号：US20220238545A1

    公开(公告)日：2022-07-28

    申请号：US17721247

    申请日：2022-04-14

    Applicant: SunRise Memory Corporation

    Inventor： Eli Harari ,  Raul Adrian Cernea

    IPC: H01L27/11578 ,  G11C7/18 ,  H03K19/20 ,  H03K19/1776 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

    Abstract: A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared hit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

    3-Dimensional NOR Strings with Segmented Shared Source Regions
    5.
    发明申请
    3-Dimensional NOR Strings with Segmented Shared Source Regions 审中-公开

    公开(公告)号：US20200185404A1

    公开(公告)日：2020-06-11

    申请号：US16792808

    申请日：2020-02-17

    Applicant: Sunrise Memory Corporation

    Inventor： Eli Harari ,  Raul Adrian Cernea

    IPC: H01L27/11578 ,  G11C16/04 ,  H03K19/1776 ,  H03K19/20 ,  G11C7/18 ,  G11C16/24 ,  G11C16/08

    Abstract: A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

    Quasi-volatile memory with enhanced sense amplifier operation
    7.
    发明授权
    Quasi-volatile memory with enhanced sense amplifier operation 有权

    公开(公告)号：US11848056B2

    公开(公告)日：2023-12-19

    申请号：US17529083

    申请日：2021-11-17

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Raul Adrian Cernea

    IPC: G11C16/26 ,  G11C16/08 ,  G11C16/24

    CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/24

    Abstract: A semiconductor memory device is implemented as a string of storage transistors with sense amplifier connected drain terminals and floating source terminals. In some embodiments, a method in the semiconductor memory device applies a bit line control (BLC) voltage with a voltage step down to the bias device during the read operation to reduce the settling time on the bit line, thereby shortening the access time for data read out from the storage transistors. In other embodiments, a method in the semiconductor memory device including an array of strings of storage transistors uses a current from a biased but unselected bit line as the sense amplifier reference current for reading stored data from a selected bit line. In one embodiment, the sense amplifier reference current is provided to a referenced sense amplifier to generate a sense amplifier data latch signal.

    Memory System Implementing Write Abort Operation For Reduced Read Latency
    8.
    发明公开
    Memory System Implementing Write Abort Operation For Reduced Read Latency 审中-公开

    公开(公告)号：US20230195314A1

    公开(公告)日：2023-06-22

    申请号：US18059971

    申请日：2022-11-29

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Masahiro Yoshihara ,  Tz-Yi Liu ,  Raul Adrian Cernea ,  Shay Fux ,  Erez Landau ,  Sagie Goldenberg

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A memory system including a memory device of storage transistors organized in multiple memory banks where the memory device interacts with a controller device to perform read and write operations. In some embodiments, the controller device is configured to issue to the memory device a write command and a write termination command, where the write command causing the memory device to initiate a write operation in the memory device and the write termination command causing the memory device to terminate the write operation. In one embodiment, the controller device issues a write abort command as the write termination command to terminate a write operation in progress at a certain memory bank of the memory device in order to issue a read command to read data from the same memory bank. The terminated write operation can resume after the completion of the read operation.

    QUASI-VOLATILE MEMORY WITH ENHANCED SENSE AMPLIFIER OPERATION
    9.
    发明申请
    QUASI-VOLATILE MEMORY WITH ENHANCED SENSE AMPLIFIER OPERATION 有权

    公开(公告)号：US20220180943A1

    公开(公告)日：2022-06-09

    申请号：US17529083

    申请日：2021-11-17

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： Raul Adrian Cernea

    IPC: G11C16/26 ,  G11C16/24 ,  G11C16/08

    Abstract: A semiconductor memory device is implemented as a string of storage transistors with sense amplifier connected drain terminals and floating source terminals. In some embodiments, a method in the semiconductor memory device applies a bit line control (BLC) voltage with a voltage step down to the bias device during the read operation to reduce the settling time on the bit line, thereby shortening the access time for data read out from the storage transistors. In other embodiments, a method in the semiconductor memory device including an array of strings of storage transistors uses a current from a biased but unselected bit line as the sense amplifier reference current for reading stored data from a selected bit line. In one embodiment, the sense amplifier reference current is provided to a referenced sense amplifier to generate a sense amplifier data latch signal.

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