中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

77 records (took 0.062 seconds)

    Method of manufacturing semiconductor device
    21.
    发明申请
    Method of manufacturing semiconductor device 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20050148138A1

    公开(公告)日：2005-07-07

    申请号：US10961767

    申请日：2004-10-07

    Applicant: Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

    Inventor： Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

    IPC: H01L21/283 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11568 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/115

    Abstract: A method of manufacturing a semiconductor device that has a high-breakdown-voltage transistor, a low-voltage driving transistor and a MONOS type memory transistor includes a step of forming a stack film that includes at least an oxide silicon layer and a nitride silicon layer over a high-breakdown-voltage transistor forming region where the high-breakdown-voltage transistor is formed, a low-voltage driving transistor forming region where the low-voltage driving transistor is formed and a MONOS type memory transistor forming region where the MONOS type memory transistor is formed in a semiconductor layer, a step of removing the stack film formed in a first gate insulating layer forming region of the high-breakdown-voltage transistor and a step of forming a first gate insulating layer in the high-breakdown-voltage transistor forming region by thermal oxidation. The method also includes a step of removing the stack film formed in the low-voltage driving transistor forming region, a step of forming a second gate insulating layer in the low-voltage driving transistor forming region, a step of forming gate electrodes in the high-breakdown-voltage transistor forming region, the low-voltage driving transistor forming region and the MONOS type memory transistor forming region and a step of forming source/drain regions in the high-breakdown-voltage transistor forming region, the low-voltage driving transistor forming region and the MONOS type memory transistor forming region.

    Abstract translation: 制造具有高击穿电压晶体管，低电压驱动晶体管和MONOS型存储晶体管的半导体器件的方法包括形成至少包含氧化硅层和氮化硅层的堆叠膜的步骤 通过形成高击穿电压晶体管的高击穿电压晶体管形成区域，形成低电压驱动晶体管的低电压驱动晶体管形成区域和MONOS型存储晶体管形成区域 存储晶体管形成在半导体层中，去除形成在高击穿电压晶体管的第一栅极绝缘层形成区域中的堆叠膜的步骤和形成高击穿电压的第一栅极绝缘层的步骤 晶体管形成区域通过热氧化。 该方法还包括去除在低电压驱动晶体管形成区域中形成的叠层膜的步骤，在低电压驱动晶体管形成区域中形成第二栅极绝缘层的步骤，在高电压驱动晶体管形成区域中形成栅电极的步骤 低电压驱动晶体管形成区域和MONOS型存储晶体管形成区域，以及在高击穿电压晶体管形成区域中形成源极/漏极区域的步骤，低电压驱动晶体管形成区域 形成区域和MONOS型存储晶体管形成区域。

    Nonvolatile semiconductor memory device and control method thereof
    22.
    发明申请
    Nonvolatile semiconductor memory device and control method thereof 有权
    非易失性半导体存储器件及其控制方法

    公开(公告)号：US20050088897A1

    公开(公告)日：2005-04-28

    申请号：US10929920

    申请日：2004-08-31

    Applicant: Susumu Inoue

    Inventor： Susumu Inoue

    IPC: G11C16/02 ,  G11C15/00 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: G11C16/3418 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3427

    Abstract: To provide a nonvolatile semiconductor memory device in which a disturb voltage onto a non-selected memory cell in writing operation is lessened, a nonvolatile semiconductor memory device, includes: a memory cell array equipped with a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines; a word line control circuit to control the plurality of word lines; and a line control circuit to control the plurality of bit lines and the plurality of source lines. Each of the plurality of memory cells is equipped with a gate electrode, a first impurity region, a second impurity region, and an electron trap region, which is positioned between the gate electrode and a substrate, and is formed at least at the first impurity region side of both the first impurity region and second impurity region. At the time when a writing operation is performed for a selected memory cell, the word line control circuit provides a selected word line connected to the selected memory cell with a selection voltage, provides a non-selected word line with a first mis-erasing prevention voltage, and provides a source line that is not connected to the selected memory cell with a second mis-erasing prevention voltage.

    Abstract translation: 为了提供一种非易失性半导体存储器件，其中写入操作中的非选择存储单元上的干扰电压减小，非易失性半导体存储器件包括：配备有多个存储单元的存储单元阵列，多个字线 ，多个位线和多个源极线; 字线控制电路，用于控制所述多个字线; 以及线路控制电路，用于控制多个位线和多条源极线。 多个存储单元中的每一个配备有位于栅电极和基板之间的栅电极，第一杂质区，第二杂质区和电子陷阱区，并且至少形成在第一杂质 区域侧的第一杂质区域和第二杂质区域。 在对所选择的存储单元进行写入操作时，字线控制电路提供与选择的存储单元连接的所选择的字线和选择电压，从而提供未选择的字线，以防止第一次错误消除 电压，并提供未连接到所选择的存储器单元的源极线，具有第二防止误擦除电压。

    Engine control system
    23.
    发明授权
    Engine control system 失效
    发动机控制系统

    公开(公告)号：US5785036A

    公开(公告)日：1998-07-28

    申请号：US718839

    申请日：1996-09-24

    Applicant: Hiroshi Ninomiya ,  Kouji Endo ,  Susumu Inoue ,  Yuji Shitani

    Inventor： Hiroshi Ninomiya ,  Kouji Endo ,  Susumu Inoue ,  Yuji Shitani

    IPC: F02M25/08 ,  F02D41/00 ,  F02D41/02 ,  F02D41/14 ,  F02D41/34 ,  F02D45/00

    CPC classification number: F02D41/1443 ,  F02D41/0042 ,  F02D41/0085 ,  F02D41/0082 ,  F02D41/1456

    Abstract: A control system for a multiple cylinder engine includes a vapor fuel introduction system for introducing a vapor fuel vaporized in a fuel tank. A feedback device is used for setting an air fuel ratio feedback compensation value for each of the cylinders or each group of cylinders of the engine and for executing an air fuel ratio feedback control. A fuel supply device is used for supplying engine fuel for each cylinder so as to equalize the air fuel ratio feedback compensation values of each of the cylinders or each group of the cylinders regardless of a change of an operating condition of a vapor fuel introduction control. A desirable A/F feedback control can be accomplished regardless of the execution of the vapor fuel purge in the multiple cylinder engine.

    Abstract translation: 用于多缸发动机的控制系统包括用于引入在燃料箱中蒸发的蒸汽燃料的蒸汽燃料引入系统。 反馈装置用于为发动机的每个气缸或每组气缸设定空燃比反馈补偿值，并用于执行空燃比反馈控制。 燃料供给装置用于为每个气缸供应发动机燃料，以便均衡每个气缸或每组气缸的空燃比反馈补偿值，而与蒸汽燃料引入控制的运行状态的变化无关。 可以实现所需的A / F反馈控制​​，而不管在多缸发动机中执行蒸汽燃料吹扫。

    Fluorine-Containing Polymer and Anti-Static Agent Wherein Same is Used
    28.
    发明申请
    Fluorine-Containing Polymer and Anti-Static Agent Wherein Same is Used 有权
    含氟聚合物和防静电剂，其中使用相同的

    公开(公告)号：US20110065857A1

    公开(公告)日：2011-03-17

    申请号：US12992035

    申请日：2009-06-10

    Applicant: Yoshiharu Terui ,  Haruhiko Komoriya ,  Susumu Inoue ,  Takashi Kume

    Inventor： Yoshiharu Terui ,  Haruhiko Komoriya ,  Susumu Inoue ,  Takashi Kume

    IPC: C08L27/12 ,  C08F14/18

    CPC classification number: C09K3/16 ,  C08F20/24 ,  C08F20/38 ,  C08F212/14 ,  C08F220/38 ,  C08L33/16 ,  Y10T428/3154 ,  Y10T428/31649

    Abstract: There is provided a fluorine-containing polymer having a repeating unit of the general formula (2) and produced by homopolymerization or copolymerization with an other polymerizable double bond-containing monomer. In the formula, W represents a linking group; R1 each independently represents a perfluoroalkyl group; Q represents a unit structure formed by cleavage of a double bond of a polymerizable double bond-containing group; and M+ represents a hydrogen cation, a metal ion or a quaternary ammonium ion.There is also provided an antistatic agent using the above fluorine-containing polymer such that the antistatic agent can impart antistatic performance to an article stably over a long time and show excellent transparency.

    Abstract translation: 提供具有通式（2）的重复单元并通过与其它可聚合双键的单体均聚或共聚制备的含氟聚合物。 在该式中，W表示连接基团; R1各自独立地表示全氟烷基; Q表示通过裂解含可聚合双键的双键的双键形成的单元结构; M +表示氢阳离子，金属离子或季铵离子。 还提供了使用上述含氟聚合物的抗静电剂，使得抗静电剂能够长时间稳定地赋予制品抗静电性能并且显示出优异的透明性。

    Semiconductor device
    29.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07253462B2

    公开(公告)日：2007-08-07

    申请号：US11249253

    申请日：2005-10-13

    Applicant: Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

    Inventor： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

    IPC: H01L31/113

    CPC classification number: H01L31/02164 ,  H01L23/552 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.

    Abstract translation: 一种半导体器件包括设置在半导体层上的半导体元件，围绕半导体元件设置的遮光壁，设置在遮光壁上的孔，以及电连接到 半导体元件并且通过孔被拉出到遮光壁的外部。 布线层具有图案，其包括位于孔内的第一部分和位于孔的外侧的第二部分，并且与第一部分的宽度相比具有较大的宽度，第二部分的宽度为 与孔的宽度相同或大于孔的宽度。

    Semiconductor device
    30.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20060170030A1

    公开(公告)日：2006-08-03

    申请号：US11330870

    申请日：2006-01-12

    Applicant: Yutaka Maruo ,  Susumu Inoue ,  Yo Takeda

    Inventor： Yutaka Maruo ,  Susumu Inoue ,  Yo Takeda

    IPC: H01L29/788

    CPC classification number: H01L27/11521 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11558

    Abstract: A semiconductor device includes: a semiconductor layer; a first area and a second area which are demarcated by a separation insulating layer provided on the semiconductor layer; a nonvolatile memory provided on the first area; a plurality of MOS transistors provided on the second area; a first interlayer insulating layer embedded between the plurality of MOS transistors on the second area; and a second interlayer insulating layer provided above the first area and the second area. The second interlayer insulating layer is provided as if covering the nonvolatile memory on the first area and, on the second area, provided, being above the first interlayer insulating layer, as if covering the MOS transistor.

    Abstract translation: 半导体器件包括：半导体层; 第一区域和第二区域，其由设置在所述半导体层上的分离绝缘层划定; 设置在所述第一区域上的非易失性存储器; 设置在所述第二区域上的多个MOS晶体管; 嵌入在所述第二区域上的所述多个MOS晶体管之间的第一层间绝缘层; 以及设置在所述第一区域和所述第二区域上方的第二层间绝缘层。 第二层间绝缘层被设置为如同覆盖第一区域上的非易失性存储器，并且在第二区域上设置在第一层间绝缘层的上方，就像覆盖MOS晶体管一样。

Patent Agency Ranking