利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

27 条记录 (耗时 0.021 秒)

    Stable SRAM cell
    21.
    发明授权
    Stable SRAM cell 有权

    公开(公告)号：US08908409B2

    公开(公告)日：2014-12-09

    申请号：US14285410

    申请日：2014-05-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Huai-Ying Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

    IPC分类号： G11C15/00 ,  G11C11/412

    CPC分类号： G11C11/412 ,  G11C11/419

    摘要： SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

    Stable SRAM Cell
    22.
    发明申请
    Stable SRAM Cell 有权

    公开(公告)号：US20140254248A1

    公开(公告)日：2014-09-11

    申请号：US14285410

    申请日：2014-05-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Huai-Ying Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

    IPC分类号： G11C11/412

    CPC分类号： G11C11/412 ,  G11C11/419

    摘要： SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

    Semiconductor memory structure
    23.
    发明授权
    Semiconductor memory structure 有权

    公开(公告)号：US11792977B2

    公开(公告)日：2023-10-17

    申请号：US17320049

    申请日：2021-05-13

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hsin-Wen Su ,  Shih-Hao Lin ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

    IPC分类号： H10B20/20

    CPC分类号： H10B20/20

    摘要： A semiconductor device includes a program word line and a read word line over an active region. Each of the program word line and the read word line extends along a line direction. Moreover, the program word line engages a first transistor channel and the read word line engages a second transistor channel. The semiconductor device also includes a first metal line over and electrically connected to the program word line and a second metal line over and electrically connected to the read word line. The semiconductor device further includes a bit line over and electrically connected to the first active region. Additionally, the program word line has a first width along a channel direction perpendicular to the line direction; the read word line has a second width along the channel direction; and the first width is less than the second width.

    INTEGRATED CIRCUIT DEVICE WITH REDUCED VIA RESISTANCE
    24.
    发明申请
    INTEGRATED CIRCUIT DEVICE WITH REDUCED VIA RESISTANCE 有权

    公开(公告)号：US20230062162A1

    公开(公告)日：2023-03-02

    申请号：US17461322

    申请日：2021-08-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jui-Lin Chen ,  Yu-Kuan Lin ,  Ping-Wei Wang

    IPC分类号： H01L27/11 ,  H01L23/528 ,  H01L27/088

    摘要： A device includes a substrate, a contact, a first gate, a second gate, a dielectric feature between the gates, a via, and a conductive line. The gates are each adjacent the contact and aligned lengthwise with each other along a first direction. A first sidewall of the dielectric feature defines an end-wall of the first gate. A second sidewall of the dielectric feature defines an end-wall of the second gate. The conductive line extends along a second direction. A projection of the conductive line onto a top surface of the dielectric feature passes between the first and second sidewalls. The via interfaces with the contact along a second plane. The via has a first dimension on the second plane along the second direction; the contact has a second dimension on the second plane along the second direction. The first dimension is greater than the second dimension.