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公开(公告)号：US11444197B2
公开(公告)日：2022-09-13
申请号：US16785247
申请日：2020-02-07
IPC分类号： H01L29/78 , H01L29/06 , H01L29/417 , H01L27/088 , H01L29/66 , H01L29/16
摘要： A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.
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公开(公告)号：US20210249530A1
公开(公告)日：2021-08-12
申请号：US16785247
申请日：2020-02-07
IPC分类号： H01L29/78 , H01L29/06 , H01L29/417 , H01L29/16 , H01L29/66 , H01L27/088
摘要： A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.
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3.发明授权公开(公告)号：US11600625B2
公开(公告)日：2023-03-07
申请号：US16949103
申请日：2020-10-14
发明人： Chih-Chuan Yang , Chia-Hao Pao , Wen-Chun Keng , Lien Jung Hung , Ping-Wei Wang
IPC分类号： H01L27/092 , H01L27/11 , H01L29/08 , H01L29/66
摘要： A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.
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公开(公告)号：US20230046028A1
公开(公告)日：2023-02-16
申请号：US17401151
申请日：2021-08-12
发明人： Chia-Hao Pao , Chih-Chuan Yang , Shih-Hao Lin , Chih-Hsuan Chen , Kian-Long Lim , Chao-Yuan Chang , Feng-Ming Chang , Lien Jung Hung , Ping-Wei Wang
IPC分类号： H01L27/11 , H01L29/06 , H01L29/423 , H01L29/786 , G06F30/392
摘要： SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a β ratio of an SRAM cell.
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公开(公告)号：US20220336480A1
公开(公告)日：2022-10-20
申请号：US17854809
申请日：2022-06-30
发明人： Hsin-Wen Su , Lien Jung Hung , Ping-Wei Wang , Yu-Kuan Lin , Shih-Hao Lin
IPC分类号： H01L27/112 , G11C17/14 , H01L21/8234 , H01L29/66 , H01L23/525
摘要： In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.
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公开(公告)号：US20220173098A1
公开(公告)日：2022-06-02
申请号：US17673030
申请日：2022-02-16
发明人： Hsin-Wen Su , Lien Jung Hung , Ping-Wei Wang , Wen-Chun Keng , Chih-Chuan Yang , Shih-Hao Lin
IPC分类号： H01L27/092 , H01L29/08 , H01L29/10 , H01L21/8238 , H01L29/423
摘要： Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.
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7.发明申请公开(公告)号：US20220115387A1
公开(公告)日：2022-04-14
申请号：US16949103
申请日：2020-10-14
发明人： Chih-Chuan Yang , Chia-Hao PAO , Wen-Chun Keng , Lien Jung Hung , Ping-Wei Wang
摘要： A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.
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公开(公告)号：US20240153949A1
公开(公告)日：2024-05-09
申请号：US18404234
申请日：2024-01-04
发明人： Hsin-Wen Su , Lien Jung Hung , Ping-Wei Wang , Wen-Chun Keng , Chih-Chuan Yang , Shih-Hao Lin
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L27/0921 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823892 , H01L27/0924 , H01L29/0847 , H01L29/1083 , H01L29/4238
摘要： Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.
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公开(公告)号：US20230197802A1
公开(公告)日：2023-06-22
申请号：US17832597
申请日：2022-06-04
发明人： Jui-Lin Chen , Chao-Hsun Wang , Hsin-Wen Su , Yi-Feng Ting , Chi Hua Wang , I-Hung Li , Yuan-Tien Tu , Fu-Kai Yang , Mei-Yun Wang , Ping-Wei Wang , Lien Jung Hung
IPC分类号： H01L29/417 , H01L27/088 , H01L21/8238
CPC分类号： H01L29/41775 , H01L27/0886 , H01L21/823821 , H01L21/823814 , H01L21/823864 , H01L29/42392
摘要： A method according to the present disclosure includes forming a fin-shaped structure protruding from a substrate, forming a gate structure intersecting the fin-shaped structure, forming a gate spacer on a sidewall of the gate structure, and forming a conductive feature above the fin-shaped structure. The gate spacer is laterally between the gate structure and the conductive feature. The method also includes depositing a dielectric layer over the gate structure and the conductive feature, performing an etching process, thereby forming an opening through the dielectric layer and exposing top surfaces of the conductive feature and the gate structure, recessing the gate spacers through the opening, thereby exposing the sidewall of the gate structure, and forming a contact feature in the opening, wherein the contact feature is in contact with the conductive feature and has a bottom portion protruding downward to be in contact with the sidewall of the gate structure.
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公开(公告)号：US12016169B2
公开(公告)日：2024-06-18
申请号：US17842208
申请日：2022-06-16
发明人： Ping-Wei Wang , Lien Jung Hung , Kuo-Hsiu Hsu , Kian-Long Lim , Yu-Kuan Lin , Chia-Hao Pao , Chih-Chuan Yang , Shih-Hao Lin , Choh Fei Yeap
IPC分类号： H01L23/528 , G11C11/412 , G11C11/419 , H01L21/66 , H04N21/426 , H10B10/00 , H10B41/35
CPC分类号： H10B10/12 , G11C11/412 , G11C11/419 , H01L22/12 , H01L23/528 , H04N21/42692 , H10B10/00 , H10B41/35 , G11C2213/74 , G11C2213/79 , H01L2924/1437
摘要： A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.
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