公开(公告)号：US11184000B2

公开(公告)日：2021-11-23

申请号：US16001551

申请日：2018-06-06

Applicant: Texas Instruments Incorporated

Inventor： Eung Jung Kim ,  Sualp Aras ,  Abidur Rahman

IPC: H03K17/082 ,  H03K17/14 ,  G01R1/067 ,  H03K17/0814 ,  H03K17/16 ,  H03K17/0812 ,  G01R31/26

Abstract: Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.

公开(公告)号：US20190214980A1

公开(公告)日：2019-07-11

申请号：US16001551

申请日：2018-06-06

Applicant: Texas Instruments Incorporated

Inventor： Eung Jung Kim ,  Sualp Aras ,  Abidur Rahman

IPC: H03K17/082 ,  H03K17/14 ,  G01R1/067 ,  G01R31/26 ,  H03K17/16 ,  H03K17/0812 ,  H03K17/0814

Abstract: Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.

公开(公告)号：US20170179278A1

公开(公告)日：2017-06-22

申请号：US15248521

申请日：2016-08-26

Applicant: Texas Instruments Incorporated

Inventor： David J Baldwin ,  Gary Eugene Daum ,  Simon John Molloy ,  Abidur Rahman

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/762 ,  H01L21/763 ,  H01L27/02 ,  H01L21/225

CPC classification number: H01L29/7815 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0266 ,  H01L27/027 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66719 ,  H01L29/7811

Abstract: A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors including a current sensor, a high current fault sensor, and a temperature sensor. The structure of the power FET includes a drain contact region of a first conductivity type disposed in the substrate, a drain drift region of the first conductivity type disposed over the drain contact region, doped polysilicon trenches disposed in the drain drift region, a body region of a second conductivity type, opposite from the first conductivity type, disposed between the doped polysilicon trenches, a source region disposed on a lateral side of the doped polysilicon trenches and in contact with the body region, and a source contact trench that makes contact with the source region and with the doped polysilicon trenches.

公开(公告)号：US20150015323A1

公开(公告)日：2015-01-15

申请号：US13942182

申请日：2013-07-15

Applicant: Texas Instruments Incorporated

Inventor： Abidur Rahman ,  Jacob Wayne Day

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M2003/076

Abstract: A charge pump circuit includes a plurality of serially coupled stages and a plurality of clock drivers. A voltage output of a first of the stages is connected to a voltage input of a second of the stages. A voltage output of the second of the stages is boosted relative to a voltage input of the second of the stages. Each of the stages includes complementary charge pumps. Each of the charge pumps includes a pumping capacitor that stores charge in the stage. Each of the clock drivers drives a clock signal to the pumping capacitor of at least one of the stages. A voltage of the clock signal provided to the second of the stages is derived from the voltage input of the second of the stages.

Abstract translation: 电荷泵电路包括多个串联耦合级和多个时钟驱动器。 第一级的电压输出连接到第二级的电压输入。 第二级的电压输出相对于第二级的电压输入被提升。 每个阶段都包括补充电荷泵。 每个电荷泵包括在电池中存储电荷的泵送电容器。 每个时钟驱动器驱动至少一个级的泵浦电容器的时钟信号。 提供给第二级的时钟信号的电压从第二级的电压输入导出。

公开(公告)号：US20140254235A1

公开(公告)日：2014-09-11

申请号：US13785583

申请日：2013-03-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abidur Rahman ,  Tatsuyuki Nihei ,  Tatsuro Sato ,  Uchino Osamu

IPC: G11C5/14

CPC classification number: G11C5/148 ,  G11C11/2297

Abstract: Corruption of data in a FRAM (2) is avoided by applying a regulated voltage (VLDO) to a conductive pin (5-1). A switch (SW1) is coupled between the conductive pin and a power terminal of the FRAM so a FRAM supply voltage (VFRAM) is equal to the regulated voltage when the switch is closed. The conductive pin is coupled to a power terminal of a digital circuit (3) so a digital circuit supply voltage (VCORE) is equal to the regulated voltage. A power interruption is detected to produce an interruption signal (nBORdet) that opens the switch and also prevents starting of new read and write operations in the FRAM. A sufficient FRAM supply voltage is maintained by an internal capacitor (CINT) while ongoing read and write operations in the FRAM are completed during a predetermined interval. The conductive pin may be coupled to the switch by bonding wire inductance (LWIRE) between the switch and the conductive pin to inhibit flow of transient currents between them.

Abstract translation: 通过将调节电压（VLDO）施加到导电针（5-1）来避免FRAM（2）中的数据损坏。 开关（SW1）耦合在导电引脚和FRAM的电源端子之间，因此当开关闭合时，FRAM电源电压（VFRAM）等于调节电压。 导电引脚耦合到数字电路（3）的电源端子，因此数字电路电源电压（VCORE）等于调节电压。 检测到电源中断以产生打开该开关的中断信号（nBORdet），并且还防止在FRAM中启动新的读取和写入操作。 在FRAM中进行的读写操作在预定间隔内完成时，由内部电容器（CINT）维持足够的FRAM电源电压。 可以通过在开关和导电引脚之间接合线电感（LWIRE）来将导电引脚耦合到开关，以抑制它们之间的瞬态电流的流动。