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21.发明授权公开(公告)号：US11960567B2
公开(公告)日：2024-04-16
申请号：US17367389
申请日：2021-07-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Arthur John Redfern , Timothy David Anderson , Kai Chirca , Chenchi Luo , Zhenhua Yu
CPC classification number: G06F17/16 , G06F17/141 , G06N3/045 , G06N3/063
Abstract: A method for performing a fundamental computational primitive in a device is provided, where the device includes a processor and a matrix multiplication accelerator (MMA). The method includes configuring a streaming engine in the device to stream data for the fundamental computational primitive from memory, configuring the MMA to format the data, and executing the fundamental computational primitive by the device.
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公开(公告)号：US10979070B2
公开(公告)日：2021-04-13
申请号：US16899632
申请日：2020-06-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Arthur John Redfern , Dan Wang
Abstract: A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed. The system implements LDC using a 2D-to-1D transformation of 2D uncompressed data blocks (2DU) within LDM to generate 1D uncompressed data blocks (1DU). The 1DU is then compressed to generate a 1D compressed superblock (CSB) in LDM. This LDM CSB may then be written to EDM with a reduced number of EDM bus cycles. The system implements LDD using decompression of CSB data retrieved from EDM to generate a 1D decompressed data block (1DD) in LDM. A 1D-to-2D transformation is then applied to the LDM 1DD to generate a 2D decompressed data block (2DD) in LDM. This 2DD may then be operated on by a matrix compute engine (MCE) using a variety of function operators.
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公开(公告)号：US20210034277A1
公开(公告)日：2021-02-04
申请号：US17072259
申请日：2020-10-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Arthur John Redfern , Asheesh Bhadwaj
Abstract: A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.
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公开(公告)号：US10809978B2
公开(公告)日：2020-10-20
申请号：US15995647
申请日：2018-06-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Arthur John Redfern , Asheesh Bhardwaj , Tarek Aziz Lahlou , William Franklin Leven
Abstract: A merge sort accelerator (MSA) includes a pre-processing stage configured to receive an input vector and generate a pre-processing output vector based on a pre-processing instruction and the input vector. The MSA also includes a merge sort network having multiple sorting stages configured to be selectively enabled. The merge sort network is configured to receive the pre-processing output vector and generate a sorted output vector based on a sorting instruction and the pre-processing output vector. The MSA includes an accumulator stage configured to receive the sorted output vector and update an accumulator vector based on the accumulator instruction and the sorted output vector. The MSA also includes a post-processing stage configured to receive the accumulator vector and generate a post-processing output vector based on a post-processing instruction and the accumulator vector.
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公开(公告)号：US10735023B2
公开(公告)日：2020-08-04
申请号：US15900611
申请日：2018-02-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Arthur John Redfern , Dan Wang
Abstract: A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed. The system implements LDC using a 2D-to-1D transformation of 2D uncompressed data blocks (2DU) within LDM to generate 1D uncompressed data blocks (1DU). The 1DU is then compressed to generate a 1D compressed superblock (CSB) in LDM. This LDM CSB may then be written to EDM with a reduced number of EDM bus cycles. The system implements LDD using decompression of CSB data retrieved from EDM to generate a 1D decompressed data block (1DD) in LDM. A 1D-to-2D transformation is then applied to the LDM 1DD to generate a 2D decompressed data block (2DD) in LDM. This 2DD may then be operated on by a matrix compute engine (MCE) using a variety of function operators.
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Patent Agency Ranking
公开(公告)号：US20180248562A1
公开(公告)日：2018-08-30
申请号：US15900611
申请日：2018-02-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Arthur John Redfern , Dan Wang
Abstract: A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed. The system implements LDC using a 2D-to-1D transformation of 2D uncompressed data blocks (2DU) within LDM to generate 1D uncompressed data blocks (1DU). The 1DU is then compressed to generate a 1D compressed superblock (CSB) in LDM. This LDM CSB may then be written to EDM with a reduced number of EDM bus cycles. The system implements LDD using decompression of CSB data retrieved from EDM to generate a 1D decompressed data block (1DD) in LDM. A 1D-to-2D transformation is then applied to the LDM 1DD to generate a 2D decompressed data block (2DD) in LDM. This 2DD may then be operated on by a matrix compute engine (MCE) using a variety of function operators.
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公开(公告)号：US09648618B2
公开(公告)日：2017-05-09
申请号：US15044171
申请日：2016-02-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Guolong Su , Arthur John Redfern
IPC: H04B1/10 , H04W72/04 , H04B17/336
CPC classification number: H04W72/0446 , H04B17/336
Abstract: A bandpass filter includes a plurality of parallel paths. Each path includes a first mixer, a low-pass filter, and a second mixer. The first mixer in each path receives the input signal and mixes the input signal with a periodic mixer sequence. The low-pass filter in each path is operable to filter an output of the associated first mixer. The second mixer in each path is coupled to receive an output of the associated low-pass filter and mixes said filter output with a periodic mixer sequence having a period that is divided into a plurality of time slots, wherein again the mixer value is constant during each time slot. A summer sums the outputs of the second mixers of each of the paths to generate an output of the bandpass filter.
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公开(公告)号：US20160043756A1
公开(公告)日：2016-02-11
申请号：US14452777
申请日：2014-08-06
Applicant: Texas Instruments Incorporated
Inventor： Guolong Su , Arthur John Redfern
IPC: H04B1/10 , H04W72/04 , H04B17/336
CPC classification number: H04W72/0446 , H04B17/336
Abstract: A bandpass filter includes a plurality of parallel paths, each receiving the input signal to the bandpass filter. Each path includes a first mixer, a low-pass filter, and a second mixer. The first mixer in each path is coupled to receive the input signal and mixes the input signal with a periodic mixer sequence having a period that is divided into a plurality of time slots. The mixer value is constant during each time slot. The low-pass filter in each path is operable to filter an output of the associated first mixer. The second mixer in each path is coupled to receive an output of the associated low-pass filter and mixes said filter output with a periodic mixer sequence having a period that is divided into a plurality of time slots, wherein again the mixer value is constant during each time slot. A summer sums the outputs of the second mixers of each of the paths to generate an output of the bandpass filter.
Abstract translation: 带通滤波器包括多个并行路径，每个并行路径将输入信号接收到带通滤波器。 每个路径包括第一混频器，低通滤波器和第二混频器。 每个路径中的第一混频器被耦合以接收输入信号，并且将输入信号与具有被划分成多个时隙的周期的周期性混频器序列混合。 混频器值在每个时隙都是恒定的。 每个路径中的低通滤波器可操作以对相关联的第一混频器的输出进行滤波。 每个路径中的第二混频器被耦合以接收相关联的低通滤波器的输出，并且将所述滤波器输出与具有被分成多个时隙的周期的周期性混频器序列混合，其中混频器值在 每个时间段 夏季对每个路径的第二混频器的输出求和，以产生带通滤波器的输出。
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公开(公告)号：US09054736B2
公开(公告)日：2015-06-09
申请号：US14100578
申请日：2013-12-09
Applicant: Texas Instruments Incorporated
Inventor： Arthur John Redfern , Kun Shi
CPC classification number: H03M3/422 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/322 , H03M3/468 , H04B1/40
Abstract: An analog to digital converter receives an analog input signal. The analog input signal is converted into a digital output signal. The converting includes shaping quantization noise in response to: a signal-to-noise ratio of the analog input signal; and a power of the converter.
Abstract translation: 模数转换器接收模拟输入信号。 模拟输入信号被转换为数字输出信号。 转换包括响应于模拟输入信号的信噪比而整形量化噪声; 和转换器的电源。
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公开(公告)号：US20140375594A1
公开(公告)日：2014-12-25
申请号：US13924771
申请日：2013-06-24
Applicant: Texas Instruments Incorporated
Inventor： Arthur John Redfern
IPC: G06F3/044
CPC classification number: G06F3/044 , G06F3/0416
Abstract: A method of operating a touch screen system having a plurality of screen nodes that includes collecting touch data from the screen nodes indicative of the number of touches received by each node and determining a nonuniform sampling sequence for the touch screen based on the collected touch data.
Abstract translation: 一种操作具有多个屏幕节点的触摸屏系统的方法，包括从屏幕节点收集指示每个节点接收的触摸数量的触摸数据，并且基于所收集的触摸数据确定触摸屏的不均匀采样序列。
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