公开(公告)号：US20240345842A1

公开(公告)日：2024-10-17

申请号：US18754455

申请日：2024-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/383 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US20230297383A1

公开(公告)日：2023-09-21

申请号：US18321037

申请日：2023-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/383 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US11669330B2

公开(公告)日：2023-06-06

申请号：US17306350

申请日：2021-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/383 ,  G06F9/3004 ,  G06F9/30036 ,  G06F9/30043

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US20220408106A1

公开(公告)日：2022-12-22

申请号：US17893297

申请日：2022-08-23

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mahesh Madhukar Mehendale ,  Subrangshu Das ,  Dipan Kumar Mandal ,  Nainala Vyagrheswarudu ,  Vijayavardhan Baireddy ,  Pavan Venkata Shastry

IPC: H04N19/43

Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.

公开(公告)号：US10397591B2

公开(公告)日：2019-08-27

申请号：US14684334

申请日：2015-04-11

Applicant: Texas Instruments Incorporated

Inventor： Dipan Kumar Mandal ,  Mihir Narendra Mody ,  Mahesh Madhukar Mehendale ,  Chaitanya Satish Ghone ,  Piyali Goswami ,  Naresh Kumar Yadav ,  Hetul Sanghvi ,  Niraj Nandan

IPC: H04N19/43 ,  H04N19/42 ,  H04N19/463 ,  G06F9/38

Abstract: A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding.

公开(公告)号：US20180275878A1

公开(公告)日：2018-09-27

申请号：US15991653

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F3/0604 ,  G06F3/0647 ,  G06F3/0673 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/383

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US20170318304A1

公开(公告)日：2017-11-02

申请号：US15653561

申请日：2017-07-19

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mahesh Madhukar Mehendale ,  Subrangshu Das ,  Dipan Kumar Mandal ,  Nainala Vyagrheswarudu ,  Vijayavardhan Baireddy ,  Pavan Venkata Shastry

IPC: H04N19/43 ,  H04N19/51

Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.

公开(公告)号：US20160232641A1

公开(公告)日：2016-08-11

申请号：US15040424

申请日：2016-02-10

Applicant: Texas Instruments Incorporated

Inventor： Sanmati S. Kamath ,  Dipan Kumar Mandal ,  Wonki Choi

IPC: G06T1/20 ,  G06T5/00

CPC classification number: G06T5/00 ,  G06F17/18 ,  G06T5/20 ,  G06T2200/28 ,  G06T2207/20032 ,  H03H17/0261

Abstract: A method is disclosed for efficiently calculating a median value of a high-order array in a Single Instruction Multiple Data (SIMD) processor. Values of the high-order array are sorted vertically in each column followed by sorts on each individual row. After the sort, selective diagonal values of the sorted high-order array are used to form a low-order array to calculate the median of the high-order array. The median calculation using selective diagonal values of the high-order array in a low-order array significantly improves SIMD processor efficiency and throughput.

Abstract translation: 公开了一种用于在单指令多数据（SIMD）处理器中有效计算高阶阵列的中值的方法。 高阶数组的值在每列中垂直排列，后跟排列在每个单独的行上。 排序后，排序高阶数组的选择性对角线值用于形成低阶数组，以计算高阶数组的中位数。 使用低阶阵列中高阶阵列的选择性对角线值的中值计算显着提高了SIMD处理器的效率和吞吐量。

公开(公告)号：US20160125263A1

公开(公告)日：2016-05-05

申请号：US14931322

申请日：2015-11-03

Applicant: Texas Instruments Incorporated

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06K9/52 ,  G06T7/60

CPC classification number: G06T7/60 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3887 ,  G06F9/3891 ,  G06F17/16 ,  G06T1/20 ,  G06T2200/28

Abstract: This invention forms a block sum of picture elements employing a vector dot product instruction to sum packed picture elements and the mask producing a vector of masked horizontal picture element. The block sum is formed from plural horizontal sums via vector single instruction multiple data (SIMD) addition.

Abstract translation: 本发明通过采用向量积积指令求和打包的图像元素和产生掩蔽的水平图像元素的矢量的掩模来形成图形元素的块和。 块和通过向量单指令多数据（SIMD）加法由多个水平和形成。

公开(公告)号：US20150271512A1

公开(公告)日：2015-09-24

申请号：US14661770

申请日：2015-03-18

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mahesh Madhukar Mehendale ,  Subrangshu Das ,  Dipan Kumar Mandal ,  Nainala Vyagrheswarudu ,  Vijayavardhan Baireddy ,  Pavan Venkata Shastry

IPC: H04N19/46 ,  H04N19/51

CPC classification number: H04N19/43 ,  H04N19/51

Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.

Abstract translation: 公开了支持动态帧填充的视频硬件引擎。 视频硬件引擎包括外部存储器。 外部存储器存储参考帧。 参考帧包括多个参考像素。 运动估计（ME）引擎接收当前LCU（最大编码单元），并且定义当前LCU周围的运动估计周围的搜索区域。 ME引擎接收与当前LCU对应的一组参考像素。 从外部存储器接收多个参考像素的参考像素集合。 当搜索区域的一部分区域在参考帧之外时，ME引擎沿着参考帧的边缘焊接一组重复像素。