公开(公告)号：US11172172B2

公开(公告)日：2021-11-09

申请号：US15395001

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Shashank Dabral ,  Rajasekhar Allu ,  Niraj Nandan

IPC: H04N9/04 ,  G06T1/20 ,  H04N9/67

Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.

公开(公告)号：US11170464B2

公开(公告)日：2021-11-09

申请号：US16909710

申请日：2020-06-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Mihir Narendra Mody

IPC: G06F9/50 ,  G06T1/60 ,  G06F9/54

Abstract: A lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. As a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. This improves image processing pipeline delays by overlapping the operations. The vision image processor provides output image data to a circular buffer in SRAM, rather than providing it to DRAM. The lens distortion correction function operates from the image data in the circular buffer. By operating from the SRAM circular buffer, access to the DRAM for the highly fragmented backmapping image data read operations is removed, improving available DRAM bandwidth. By using a circular buffer, less space is needed in the SRAM. The improved memory operations further improve the image processing pipeline delays.

公开(公告)号：US11070819B2

公开(公告)日：2021-07-20

申请号：US16564871

申请日：2019-09-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/176 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/117 ,  H04N19/186

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

公开(公告)号：US10949357B2

公开(公告)日：2021-03-16

申请号：US16256821

申请日：2019-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Gregory Raymond Shurtz ,  Mihir Narendra Mody ,  Charles Lance Fuoco ,  Donald E. Steiss ,  Jonathan Elliot Bergsagel ,  Jason A. T. Jones

IPC: G06F12/1027 ,  G06F9/455 ,  G06F12/1036

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US10929209B2

公开(公告)日：2021-02-23

申请号：US16377404

申请日：2019-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish Chitnis ,  Charles Lance Fuoco ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  William A. Mills ,  Gregory Raymond Shurtz ,  Amritpal Singh Mundra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

公开(公告)号：US10891717B2

公开(公告)日：2021-01-12

申请号：US16178200

申请日：2018-11-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Shashank Dabral ,  Jesse Gregory Villarreal, Jr. ,  William Wallace ,  Niraj Nandan

IPC: G06K9/00 ,  G06T5/00 ,  G06T5/20 ,  G06K9/46

Abstract: A method for filtering noise for imaging includes receiving an image frame having position and range data. A filter size divides the frame into filter windows for processing each of the filter windows. For the first pixel, a space to the center pixel and a range difference between this pixel and the center pixel is determined and used for choosing a selected weight from weights in a 2D weight LUT including weighting for space and range difference, a filtered range value is calculated by applying the selected 2D weight to the pixel, and the range, filtered range value and selected 2D weight are summed. The determining, choosing, calculating and summing are repeated for at least the second pixel. A total sum of contributions from the first and second pixel are divided by the sum of selected 2D weights to generate a final filtered range value for the center pixel.

公开(公告)号：US10824934B2

公开(公告)日：2020-11-03

申请号：US15784588

申请日：2017-10-16

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Shyam Jagannathan ,  Manu Mathew ,  Jason T. Jones

IPC: G06N3/04 ,  G06F17/16 ,  G06F7/52 ,  G06F7/544 ,  G06N3/063 ,  G06N3/08

Abstract: Described examples include an integrated circuit including a vector multiply unit including a plurality of multiply/accumulate nodes, in which the vector multiply unit is operable to provide an output from the multiply/accumulate nodes, a first data feeder operable to provide first data to the vector multiply unit in vector format, and a second data feeder operable to provide second data to the vector multiply unit in vector format.

公开(公告)号：US10810281B2

公开(公告)日：2020-10-20

申请号：US16057667

申请日：2018-08-07

Applicant: Texas Instruments Incorporated

Inventor： Arthur John Redfern ,  Donald Edward Steiss ,  Mihir Narendra Mody ,  Tarek Aziz Lahlou

IPC: G06F17/16 ,  G06F9/30 ,  G06F7/78 ,  G06F7/544

Abstract: An outer product multiplier (GPM) system/method that integrates compute gating and input/output circular column rotation functions to balance time spent in compute and data transfer operations while limiting overall dynamic power dissipation is disclosed. Matrix compute gating (MCG) based on a computation decision matrix (CDM) limits the number of computations required on a per cycle basis to reduce overall matrix compute cycle power dissipation. A circular column rotation vector (CRV) automates input/output data formatting to reduce the number of data transfer operations required to achieve a given matrix computation result. Matrix function operators (MFO) utilizing these features are disclosed and include: matrix-matrix multiplication; matrix-matrix and vector-vector point-wise multiplication, addition, and assignment; matrix-vector multiplication; vector-vector inner product; matrix transpose; matrix row permute; and vector-column permute.

公开(公告)号：US10715815B2

公开(公告)日：2020-07-14

申请号：US16432453

申请日：2019-06-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hrushikesh Tukaram Garud ,  Mihir Narendra Mody ,  Soyeb Nagori

IPC: H04N19/31 ,  H04N19/147 ,  H04N19/117 ,  H04N19/182 ,  H04N19/149 ,  H04N19/82 ,  H04N19/176

Abstract: The disclosure provides a sample adaptive offset (SAO) encoder. The SAO encoder includes a statistics collection (SC) block and a rate distortion optimization (RDO) block coupled to the SC block. The SC block receives a set of deblocked pixels and a set of original pixels. The SC block categorizes each deblocked pixel of the set of deblocked pixels in at least one of a plurality of band and edge categories. The SC block estimates an error in each category as difference between a deblocked pixel of the set of deblocked pixels and corresponding original pixel of the set of original pixels. The RDO block determines a set of candidate offsets associated with each category and selects a candidate offset with a minimum RD cost. The minimum RD cost is used by a SAO type block and a decision block to generate final offsets for the SAO encoder.

公开(公告)号：US10380746B2

公开(公告)日：2019-08-13

申请号：US15784285

申请日：2017-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Mike Lachmayr ,  Anish Reghunath ,  Rajat Sagar

IPC: G06T7/246 ,  G06T7/223

Abstract: An optical flow system includes a binary mask generation circuit and an optical flow circuit. The binary mask generation circuit is configured to receive a plurality of points of interest from a captured image that contains an array of pixels arranged as rows and columns and includes width lines that correspond to the rows and height lines that correspond to the columns. The binary mask generation circuit is also configured to generate a binary mask based on the plurality of points of interest. The binary mask includes a representation of a subset of the plurality of points of interest. The optical flow circuit is configured to receive the binary mask and generate an optical flow map of the subset of the plurality of points of interest.