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公开(公告)号：US20190043153A1
公开(公告)日：2019-02-07
申请号：US15668453
申请日：2017-08-03
Applicant: Texas Instruments Incorporated
Inventor： Sunita Nadampalli , Anish Reghunath , Brian Okchon Chae , Jonathan Elliot Bergsagel , Gregory Raymond Shurtz
IPC: G06T1/20 , G06F3/06 , G06F9/54 , H04N21/4143
CPC classification number: G06T1/20 , G06F3/0641 , G06F3/0655 , G06F9/544 , H04N21/41422 , H04N21/4143 , H04N21/42653 , H04N2005/443
Abstract: An integrated circuit includes a display sub-system that has a plurality of image processing resources and control logic. The image processing resources include a plurality of image processing pipelines configured to operate in parallel, overlay logic coupled to receive image data from the plurality of image processing pipelines, and an image output port coupled to an output of the overlay logic with image data outputs configured to couple to one or more display devices. The control logic is dynamically configurable to assign each of the image processing resources to a selected one of a first control port and a second control port. The first control port is configured to be controlled exclusively by a first processor and the second control port is configured to be controlled exclusively by a second processor.
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Patent Agency Ranking
公开(公告)号：US11693787B2
公开(公告)日：2023-07-04
申请号：US17171185
申请日：2021-02-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriramakrishnan Govindarajan , Gregory Raymond Shurtz , Mihir Narendra Mody , Charles Lance Fuoco , Donald E. Steiss , Jonathan Elliot Bergsagel , Jason A.T. Jones
IPC: G06F12/1027 , G06F9/455
CPC classification number: G06F12/1027 , G06F9/45558 , G06F2009/45583 , G06F2212/657
Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.
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公开(公告)号：US10949357B2
公开(公告)日：2021-03-16
申请号：US16256821
申请日：2019-01-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriramakrishnan Govindarajan , Gregory Raymond Shurtz , Mihir Narendra Mody , Charles Lance Fuoco , Donald E. Steiss , Jonathan Elliot Bergsagel , Jason A. T. Jones
IPC: G06F12/1027 , G06F9/455 , G06F12/1036
Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.
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公开(公告)号：US10395541B2
公开(公告)日：2019-08-27
申请号：US14874112
申请日：2015-10-02
Applicant: Texas Instruments Incorporated
Inventor： Jonathan Elliot Bergsagel , Sunita Nadampalli , Thomas Ray Shelburne , Aishwarya Dubey , Ian Carl Byers
Abstract: An integrated fault-tolerant augmented area viewing system includes, for example, a subsystem processor for receiving a safety signal for blind spot monitoring from a blind spot sensor and for generating a subsystem processor video output signal in response to the received safety signal. Selector circuitry selects the subsystem processor video output signal or a master controller video output signal received from a master controller and generates a selected video output signal in response. The selector circuitry performs the selection of the video output signal selection in response to receiving a safety request signal generated in response to a user action. A buffer outputs the selected video output signal for displaying on a display for viewing by the user.
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公开(公告)号：US10540736B2
公开(公告)日：2020-01-21
申请号：US15668453
申请日：2017-08-03
Applicant: Texas Instruments Incorporated
Inventor： Sunita Nadampalli , Anish Reghunath , Brian Okchon Chae , Jonathan Elliot Bergsagel , Gregory Raymond Shurtz
IPC: G06T1/20 , G06F3/06 , G06F9/54 , H04N21/4143 , H04N5/44
Abstract: An integrated circuit includes a display sub-system that has a plurality of image processing resources and control logic. The image processing resources include a plurality of image processing pipelines configured to operate in parallel, overlay logic coupled to receive image data from the plurality of image processing pipelines, and an image output port coupled to an output of the overlay logic with image data outputs configured to couple to one or more display devices. The control logic is dynamically configurable to assign each of the image processing resources to a selected one of a first control port and a second control port. The first control port is configured to be controlled exclusively by a first processor and the second control port is configured to be controlled exclusively by a second processor.
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公开(公告)号：US20160210861A1
公开(公告)日：2016-07-21
申请号：US14874112
申请日：2015-10-02
Applicant: Texas Instruments Incorporated
Inventor： Jonathan Elliot Bergsagel , Sunita Nadampalli , Thomas Ray Shelburne , Aishwarya Dubey , Ian Carl Byers
CPC classification number: G08G1/167 , B60Q9/008 , B60R1/00 , B60R2300/404 , B60R2300/70
Abstract: An integrated fault-tolerant augmented area viewing system includes, for example, a subsystem processor for receiving a safety signal for blind spot monitoring from a blind spot sensor and for generating a subsystem processor video output signal in response to the received safety signal. Selector circuitry selects the subsystem processor video output signal or a master controller video output signal received from a master controller and generates a selected video output signal in response. The selector circuitry performs the selection of the video output signal selection in response to receiving a safety request signal generated in response to a user action. A buffer outputs the selected video output signal for displaying on a display for viewing by the user.
Abstract translation: 集成容错增强区域查看系统包括例如子系统处理器，用于从盲点传感器接收盲点监视的安全信号，并响应于接收的安全信号产生子系统处理器视频输出信号。 选择器电路选择从主控制器接收的子系统处理器视频输出信号或主控制器视频输出信号，并响应产生选定的视频输出信号。 响应于接收到响应于用户动作产生的安全请求信号，选择器电路执行视频输出信号选择的选择。 缓冲器输出所选择的视频输出信号，以在显示器上显示以供用户查看。
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