公开(公告)号：US20180191362A1

公开(公告)日：2018-07-05

申请号：US15909378

申请日：2018-03-01

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/10 ,  H03M1/16 ,  H03M1/36

CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/1205 ,  H03M1/164 ,  H03M1/361

Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US09941893B2

公开(公告)日：2018-04-10

申请号：US15485552

申请日：2017-04-12

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/12

CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/1205 ,  H03M1/164 ,  H03M1/361

Abstract: An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US09748966B2

公开(公告)日：2017-08-29

申请号：US15231415

申请日：2016-08-08

Applicant: Texas Instruments Incorporated

Inventor： Viswanathan Nagarajan ,  Srinivas Kumar Reddy Naru ,  Ratna Kumar Venkata Parupudi

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/16

CPC classification number: H03M1/0641 ,  H03M1/168

Abstract: A system includes an analog-to-digital converter (ADC) including an ADC input terminal; an ADC output terminal; and analog components configured to convert an analog signal received at the ADC input terminal to a digital signal. The system also includes a histogram estimation circuit coupled to the ADC output terminal and configured to generate information on a plurality of codes generated by the ADC and determine a region defining a range of codes corresponding to an occurrence of an error caused by the analog components of the ADC. The system also includes a dither circuit coupled to the ADC input terminal and configured to introduce a dither in the analog signal to generate a modified analog signal.