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    ACCELEROMETER-AIDED GYROSCOPE
    21.
    发明申请
    ACCELEROMETER-AIDED GYROSCOPE 审中-公开
    加速度计激光陀螺仪

    公开(公告)号：US20140290398A1

    公开(公告)日：2014-10-02

    申请号：US14079870

    申请日：2013-11-14

    Applicant: Texas Instruments Incorporated

    Inventor： Deric W. Waters ,  Tarkesh Pande

    IPC: G01C21/16 ,  G01C19/04

    CPC classification number: G01C21/16 ,  G01C19/04 ,  Y10T74/1229

    Abstract: A method comprises computing a metric based on the accelerometer signal to remove an acceleration due to gravity. A bandwidth of a gyroscope filter is set based on the accelerometer signal and the computed metric. The gyroscope filter uses a low-pass filter to filter a signal from the gyroscope.

    Abstract translation: 一种方法包括基于加速度计信号来计算度量以消除由于重力引起的加速度。 基于加速度计信号和计算出的度量来设置陀螺仪滤波器的带宽。 陀螺仪滤波器使用低通滤波器对陀螺仪的信号进行滤波。

    Building, Transmitting, and Receiving Frame Structures in Power Line Communications
    22.
    发明申请
    Building, Transmitting, and Receiving Frame Structures in Power Line Communications 审中-公开
    电力线通信中的建筑，发射和接收帧结构

    公开(公告)号：US20140146900A1

    公开(公告)日：2014-05-29

    申请号：US14169773

    申请日：2014-01-31

    Applicant: Texas Instruments Incorporated

    Inventor： Anand G. Dabak ,  Badri N. Varadarajan ,  Il Han Kim ,  Tarkesh Pande

    IPC: H04B3/54

    CPC classification number: H04L69/22 ,  H04B3/30 ,  H04B3/54 ,  H04B3/542 ,  H04B10/11 ,  H04B2001/6912

    Abstract: Systems and methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described herein provide a preamble design using one or more symbols based on a chirp signal that yields a low peak-to-average power ratio (PAPR). According to some techniques, the preamble may be constructed with one or more different types and/or number of symbols configured to identify a PLC domain operating in close physical proximity to another PLC domain. According to other techniques, one or more preamble symbols may be interspersed within a header portion of a PLC frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise. According to yet other techniques, a PLC detector may be capable of receiving and decoding two or more types of PLC frames (e.g., using different PLC standards).

    Abstract translation: 描述了在电力线通信（PLC）中构建，发送和接收帧结构的系统和方法。 本文描述的各种技术基于产生低峰值与平均功率比（PAPR）的啁啾信号提供使用一个或多个符号的前导码设计。 根据一些技术，可以使用一个或多个不同类型和/或符号数来构造前导码，该符号被配置为识别在与另一个PLC域紧密物理接近的操作的PLC域。 根据其他技术，一个或多个前导符号可以散布在PLC帧的报头部分内，以便于例如在存在脉冲噪声的情况下估计帧边界和/或采样频率偏移。 根据其他技术，PLC检测器可能能够接收和解码两个或更多类型的PLC帧（例如，使用不同的PLC标准）。

    Bit slicer circuit for S-FSK receiver, integrated circuit, and method associated therewith
    24.
    发明授权
    Bit slicer circuit for S-FSK receiver, integrated circuit, and method associated therewith 有权

    公开(公告)号：US11265191B2

    公开(公告)日：2022-03-01

    申请号：US16944562

    申请日：2020-07-31

    Applicant: Texas Instruments Incorporated

    Inventor： Nikolaus Klemmer ,  Amneh Mohammed Akour ,  Abhijit Anant Patki ,  Timothy Patrick Pauletti ,  Tarkesh Pande

    IPC: H04L27/14 ,  H04L27/06 ,  H04B1/69

    Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

    HEART RATE ESTIMATION APPARATUS WITH STATE SEQUENCE OPTIMIZATION
    25.
    发明申请
    HEART RATE ESTIMATION APPARATUS WITH STATE SEQUENCE OPTIMIZATION 有权

    公开(公告)号：US20210378535A1

    公开(公告)日：2021-12-09

    申请号：US17412580

    申请日：2021-08-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Tarkesh Pande ,  David Patrick Magee ,  Rajan Narasimha

    IPC: A61B5/024 ,  A61B5/00

    Abstract: Disclosed examples include heart rate monitor systems and methods to estimate a patient heart rate or rate of another pulsed signal, in which rate hypotheses or states, are identified for a current time window according to digital sample values of the pulsed signal for a current sample time window, and a rate change value is computed for potential rate transitions between states of the current and previous time windows. Transition pair branch metric values are computed as a function of the rate change value and a frequency domain amplitude of the corresponding rate hypothesis for the current time window, and the pulsed signal rate estimate is determined according to a maximum path metric computed according to the branch metric value and a corresponding path metric value for the previous time window.

    Bit slicer circuit for S-FSK receiver, integrated circuit, and method associated therewith
    26.
    发明授权
    Bit slicer circuit for S-FSK receiver, integrated circuit, and method associated therewith 有权

    公开(公告)号：US11196596B2

    公开(公告)日：2021-12-07

    申请号：US17018366

    申请日：2020-09-11

    Applicant: Texas Instruments Incorporated

    Inventor： Nikolaus Klemmer ,  Amneh Mohammed Akour ,  Abhijit Anant Patki ,  Timothy Patrick Pauletti ,  Tarkesh Pande

    IPC: H04L27/06 ,  H04B1/69 ,  H04L27/14

    Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

    Heart rate estimation apparatus using digital automatic gain control
    29.
    发明授权
    Heart rate estimation apparatus using digital automatic gain control 有权

    公开(公告)号：US10758185B2

    公开(公告)日：2020-09-01

    申请号：US15203859

    申请日：2016-07-07

    Applicant: Texas Instruments Incorporated

    Inventor： Tarkesh Pande ,  David Patrick Magee

    IPC: A61B5/024 ,  A61B5/00

    Abstract: Disclosed examples include heart rate monitor systems and methods to estimate a patient heart rate, in which a processor filters digital photoplethysmogram (PPG) sample values representing transmission or reflection of a light signal in the patient during a time window, performs motion compensation processing on the filtered values, computes a gain value for individual segments of the time window using the motion compensated values, applies the individual gain values to the motion compensated values of blocks associated with the corresponding segments, and determines a heart rate estimate value representing the patient heart rate according to the frequency content of the adjusted values.

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