公开(公告)号：US09772899B2

公开(公告)日：2017-09-26

申请号：US14703714

申请日：2015-05-04

Applicant: Texas Instruments Incorporated

Inventor： Sai Zhang ,  Yuming Zhu ,  Clive Bittlestone ,  Srinath Ramaswamy

IPC: G06F11/08 ,  G11C29/52 ,  G06F11/10 ,  G06F3/06 ,  G06F12/02 ,  H03M13/13

CPC classification number: G06F11/08 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1072 ,  G06F11/1076 ,  G06F12/0246 ,  G11C29/52 ,  H03M13/13

Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a host processor is arranged to send a data word that is to be stored in a WOM (Write-Once Memory) device. A host interface is arranged to receive the first data word for processing by a WOM controller and an ECC controller. The WOM controller is for generating a first WOM-encoded word in response to an original symbol of the first data word, while the ECC controller is for generating a first set of ECC bits in response to the original symbol of the first data word. A memory device interface is for writing the first WOM-encoded word and the first set of ECC bits to the WOM device in accordance with the memory address associated with the first data word.

公开(公告)号：US09690517B2

公开(公告)日：2017-06-27

申请号：US14720442

申请日：2015-05-22

Applicant: Texas Instruments Incorporated

Inventor： Sai Zhang ,  Yuming Zhu ,  Clive Bittlestone ,  Srinath Ramaswamy

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1048 ,  G11C29/52 ,  H03M13/159 ,  H03M13/19 ,  H03M13/353 ,  H03M13/616

Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Only Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.

公开(公告)号：US20170052253A1

公开(公告)日：2017-02-23

申请号：US15225134

申请日：2016-08-01

Applicant: Texas Instruments Incorporated

Inventor： Yuming Zhu ,  Srinath Ramaswamy ,  Domingo Garcia ,  Sujeet Milind Patole

IPC: G01S15/10 ,  G01S7/521

CPC classification number: G01S15/10 ,  G01N29/07 ,  G01N29/075 ,  G01N29/11 ,  G01N29/12 ,  G01N29/14 ,  G01N2291/011 ,  G01N2291/014 ,  G01N2291/0258 ,  G01S7/539 ,  G01S15/003 ,  G01S15/582

Abstract: A transducer system with transducer and circuitry for applying a pulse train at a single frequency to excite the transducer. The transducer is operable to receive an echo waveform in response to the pulse train. The system also comprises circuitry for determining a time of flight as between a first reference time associated with the pulse train and a second reference time associated with the echo waveform.

Abstract translation: 一种具有换能器和电路的换能器系统，用于以单个频率施加脉冲串来激励换能器。 换能器可操作以响应于脉冲串接收回波波形。 该系统还包括用于在与脉冲串相关联的第一参考时间和与回波波形相关联的第二参考时间之间确定飞行时间的电路。

公开(公告)号：US09543981B2

公开(公告)日：2017-01-10

申请号：US14224960

申请日：2014-03-25

Applicant: Texas Instruments Incorporated

Inventor： Jing-Fei Ren ,  Manish Goel ,  Yuming Zhu

IPC: H03M13/00 ,  H03M13/09 ,  H04L1/00

CPC classification number: H03M13/09 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/16

Abstract: A CRC (cyclic redundancy check) generator circuit (28) generates a first CRC code based on a message. The CRC code is amended to the message, creating a first data packet. Circuitry transforms the first data packet to a second data packet for suitable transmission. Digital receiver circuitry receives the second data packet. A CRC verification circuit compares a received digital CRC code portion of the second data packet to a calculated digital CRC code portion. A message is presented for processing if no error is detected. A CRC-based FEC (forward error correction) circuit receives the message and calculates a digital CRC code from the verification circuit. When an error is detected, the detected error, based on a determination of whether the detected error affects an even number of bits or an odd number of bits, is corrected.

Abstract translation: CRC（循环冗余校验）发生器电路（28）基于消息生成第一CRC码。 将CRC码修改为消息，创建第一个数据包。 电路将第一数据分组转换为第二数据分组以进行适当的传输。 数字接收机电路接收第二数据分组。 CRC验证电路将接收到的第二数据分组的数字CRC码部分与计算出的数字CRC码部分进行比较。 如果没有检测到错误，则显示一条消息用于处理。 基于CRC的FEC（前向纠错）电路接收消息并从验证电路计算数字CRC码。 当检测到错误时，基于检测到的误差是否影响偶数位或奇数位的确定，检测到的错误被校正。

公开(公告)号：US20160342471A1

公开(公告)日：2016-11-24

申请号：US14720442

申请日：2015-05-22

Applicant: Texas Instruments Incorporated

Inventor： Sai Zhang ,  Yuming Zhu ,  Clive Bittlestone ,  Srinath Ramaswamy

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1048 ,  G11C29/52 ,  H03M13/159 ,  H03M13/19 ,  H03M13/353 ,  H03M13/616

Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Only Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.

Abstract translation: 一次写入存储器（WOM）代码的纠错码（ECC）管理系统包括例如用于在WOM（只写存储器）模式和ECC（纠错码）模式之一中进行选择的控制器。 编解码器被布置为在选择的模式下操作。 以ECC模式操作的编解码器被配置为响应于第一接收数据字的ECC奇偶校验位来识别至少一个位错误的位位置。 在WOM模式下操作的编解码器被布置成从WOM设备中的寻址位置接收WOM编码的字，以接收待编码和写入到寻址位置的第二接收数据字，并且生成WOM编码字 用于写入WOM设备中的寻址位置。 用于写入寻址位置的WOM编码字可选地被ECC编码。

公开(公告)号：US20160328289A1

公开(公告)日：2016-11-10

申请号：US14703714

申请日：2015-05-04

Applicant: Texas Instruments Incorporated

Inventor： Sai Zhang ,  Yuming Zhu ,  Clive Bittlestone ,  Srinath Ramaswamy

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/08 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1072 ,  G06F11/1076 ,  G06F12/0246 ,  G11C29/52 ,  H03M13/13

Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a host processor is arranged to send a data word that is to be stored in a WOM (Write-Only Memory) device. A host interface is arranged to receive the first data word for processing by a WOM controller and an ECC controller. The WOM controller is for generating a first WOM-encoded word in response to an original symbol of the first data word, while the ECC controller is for generating a first set of ECC bits in response to the original symbol of the first data word. A memory device interface is for writing the first WOM-encoded word and the first set of ECC bits to the WOM device in accordance with the memory address associated with the first data word.

Abstract translation: 一次写入存储器（WOM）代码的纠错码（ECC）管理系统包括例如主机处理器被配置为发送要存储在WOM（只写存储器）设备中的数据字。 主机接口被布置为接收第一数据字以供WOM控制器和ECC控制器处理。 WOM控制器用于响应于第一数据字的原始符号来生成第一WOM编码字，而ECC控制器用于响应于第一数据字的原始符号来生成第一组ECC位。 存储器件接口用于根据与第一数据字相关联的存储器地址将第一WOM编码字和第一组ECC位写入WOM器件。