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公开(公告)号：US20200083907A1
公开(公告)日：2020-03-12
申请号：US16680738
申请日：2019-11-12
发明人： Manish Goel , Yuming Zhu
摘要： Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.
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公开(公告)号：US10430494B2
公开(公告)日：2019-10-01
申请号：US15426277
申请日：2017-02-07
发明人： Kyong Ho Lee , Seok-Jun Lee , Manish Goel
摘要： Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.
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3.发明申请公开(公告)号：US20190004897A1
公开(公告)日：2019-01-03
申请号：US16122575
申请日：2018-09-05
发明人： Yuming Zhu , Manish Goel , Sai Zhang
IPC分类号： G06F11/10 , G06F11/30 , G11C29/44 , G11C29/52 , G11C29/04 , G11C16/30 , G11C16/26 , G11C29/42 , G11C11/22 , G11C29/02
摘要： In described examples, data are stored in a destructive read non-volatile memory (DRNVM). The DRNVM includes an array of DRNVM cells organized as rows of data. The rows of data are subdivided into columns of code word symbols. Each column of code word symbols is encoded to store an error correction code symbol for each column of code word symbols.
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公开(公告)号：US20170147532A1
公开(公告)日：2017-05-25
申请号：US15426277
申请日：2017-02-07
发明人： Kyong Ho Lee , Seok-Jun Lee , Manish Goel
CPC分类号： G06F17/17 , G06F7/483 , G06F7/544 , G06F9/3001
摘要： Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.
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公开(公告)号：US09606796B2
公开(公告)日：2017-03-28
申请号：US14067343
申请日：2013-10-30
发明人： Kyong Ho Lee , Seok-Jun Lee , Manish Goel
CPC分类号： G06F17/17 , G06F7/483 , G06F7/544 , G06F9/3001
摘要： Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.
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公开(公告)号：US20180217837A1
公开(公告)日：2018-08-02
申请号：US15925957
申请日：2018-03-20
发明人： Srinivas Lingam , Seok-Jun Lee , Johann Zipperer , Manish Goel
CPC分类号： G06F9/3013 , G06F9/3001 , G06F9/30036 , G06F9/30098 , G06F9/3877 , G06F9/3889 , G06F13/1678 , G06F13/4018 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.
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公开(公告)号：US09799389B2
公开(公告)日：2017-10-24
申请号：US14846350
申请日：2015-09-04
CPC分类号： G11C11/2275 , G06F11/1008 , G06F11/1068 , G11C11/221 , G11C11/2273 , G11C29/52 , G11C2029/0411 , H03M13/2945
摘要： A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B0, B1). A first data state (0) is written to a signal bit (Bi) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.
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公开(公告)号：US09543981B2
公开(公告)日：2017-01-10
申请号：US14224960
申请日：2014-03-25
发明人： Jing-Fei Ren , Manish Goel , Yuming Zhu
CPC分类号： H03M13/09 , H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/16
摘要： A CRC (cyclic redundancy check) generator circuit (28) generates a first CRC code based on a message. The CRC code is amended to the message, creating a first data packet. Circuitry transforms the first data packet to a second data packet for suitable transmission. Digital receiver circuitry receives the second data packet. A CRC verification circuit compares a received digital CRC code portion of the second data packet to a calculated digital CRC code portion. A message is presented for processing if no error is detected. A CRC-based FEC (forward error correction) circuit receives the message and calculates a digital CRC code from the verification circuit. When an error is detected, the detected error, based on a determination of whether the detected error affects an even number of bits or an odd number of bits, is corrected.
摘要翻译： CRC（循环冗余校验）发生器电路（28）基于消息生成第一CRC码。 将CRC码修改为消息，创建第一个数据包。 电路将第一数据分组转换为第二数据分组以进行适当的传输。 数字接收机电路接收第二数据分组。 CRC验证电路将接收到的第二数据分组的数字CRC码部分与计算出的数字CRC码部分进行比较。 如果没有检测到错误，则显示一条消息用于处理。 基于CRC的FEC（前向纠错）电路接收消息并从验证电路计算数字CRC码。 当检测到错误时，基于检测到的误差是否影响偶数位或奇数位的确定，检测到的错误被校正。
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公开(公告)号：US20150255138A1
公开(公告)日：2015-09-10
申请号：US14252551
申请日：2014-04-14
CPC分类号： G11C11/2275 , G06F11/1008 , G06F11/1068 , G11C11/221 , G11C11/2273 , G11C29/52 , G11C2029/0411 , H03M13/2945
摘要： A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B0, B1). A first data state (0) is written to a signal bit (Bi) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.
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10.发明授权公开(公告)号：US08897546B2
公开(公告)日：2014-11-25
申请号：US13632405
申请日：2012-10-01
发明人： Jing-Fei Ren , Manish Goel , Branislav Kisacanin
CPC分类号： G06T7/0075 , G06T7/593 , G06T7/97 , G06T2207/10021 , G06T2207/20021
摘要： A method for disparity cost computation for a stereoscopic image is provided that includes computing path matching costs for external paths of at least some boundary pixels of a tile of a base image of the stereoscopic image, wherein a boundary pixel is a pixel at a boundary between the tile and a neighboring tile in the base image, storing the path matching costs for the external paths, computing path matching costs for pixels in the tile, wherein the stored path matching costs for the external paths of the boundary pixels are used in computing some of the path matching costs of some of the pixels in the tile, and computing aggregated disparity costs for the pixels in the tile, wherein the path matching costs computed for each pixel are used to compute the aggregated disparity costs for the pixel.
摘要翻译： 提供了一种用于立体图像的视差成本计算的方法，其包括针对立体图像的基本图像的图块的至少一些边界像素的外部路径的计算路径匹配成本，其中边界像素是在 存储基本图像中的瓦片和相邻瓦片，存储外部路径的路径匹配成本，对于瓦片中的像素的计算路径匹配成本，其中，边缘像素的外部路径的存储路径匹配成本用于计算一些 的图块中的一些像素的路径匹配成本，以及计算图块中的像素的聚集的差异成本，其中为每个像素计算的路径匹配成本用于计算像素的聚集的视差成本。
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