公开(公告)号：US20230253284A1

公开(公告)日：2023-08-10

申请号：US18136500

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Wei CHENG ,  Chun-Hao Chou ,  Kuo-Cheng Lee ,  Ying-Hao Chen

IPC: H01L23/367 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L23/481 ,  H01L25/0657

Abstract: The present disclosure describes heat dissipation structures formed in functional or non- functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.

公开(公告)号：US10516048B2

公开(公告)日：2019-12-24

申请号：US15804887

申请日：2017-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： I-Chih Chen ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.

公开(公告)号：US09728637B2

公开(公告)日：2017-08-08

申请号：US14080313

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Jung-Chi Jeng ,  I-Chih Chen ,  Wen-Chang Kuo ,  Ying-Hao Chen ,  Ru-Shang Hsiao ,  Chih-Mu Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7833 ,  H01L29/0649 ,  H01L29/6659

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate.

公开(公告)号：US09728511B2

公开(公告)日：2017-08-08

申请号：US14109162

申请日：2013-12-17

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Hsi-Jung Wu ,  Volume Chien ,  Ying-Lang Wang ,  Hsin-Chi Chen ,  Ying-Hao Chen ,  Hung-Ta Huang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/58 ,  H01L21/784

CPC classification number: H01L23/562 ,  H01L21/784 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.

公开(公告)号：US20150170985A1

公开(公告)日：2015-06-18

申请号：US14109162

申请日：2013-12-17

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Hsi-Jung Wu ,  Volume Chien ,  Ying-Lang Wang ,  Hsin-Chi Chen ,  Ying-Hao Chen ,  Hung-Ta Huang

IPC: H01L23/10 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/784 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.

Abstract translation: 半导体晶片包括基板，集成电路和模具密封环结构。 基板具有模具区域，围绕模具区域的模具密封环区域和围绕模具密封环区域的划线区域。 基板包括与第一表面相对的第一表面和第二表面，以及在模具密封环区域的第一表面，划线区域或模具密封环区域和划线区域内的周期性凹槽。 集成电路位于模具区域的第一表面和第二表面上。 模具密封环结构位于模具密封环区域的第二表面上。 还提供半导体管芯。