公开(公告)号：US20210242401A1

公开(公告)日：2021-08-05

申请号：US16919071

申请日：2020-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-I Wu

IPC: H01L45/00

Abstract: A memory device and a programming method of the memory device are provided. The memory device includes a bottom electrode, a heater, a phase change layer and a top electrode. The heater is disposed on the bottom electrode, and includes heat conducting materials different from one another in terms of electrical resistivity. A first one of the heat conducting materials has a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion. A second one of the heat conducting materials is disposed on the bottom plate portion of the first one of the heat conducting materials, and laterally surrounded by the periphery wall portion of the first one of the heat conducting materials. The phase change layer is disposed on the heater and in contact with the heat conducting materials. The top electrode is disposed on the phase change layer.

公开(公告)号：US20240334708A1

公开(公告)日：2024-10-03

申请号：US18742325

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H10B51/30 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20

CPC classification number: H10B51/30 ,  H01L21/02565 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78391 ,  H10B51/20

Abstract: A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.

公开(公告)号：US11672126B2

公开(公告)日：2023-06-06

申请号：US17137768

申请日：2020-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-I Wu ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H10B51/20 ,  H01L27/11597 ,  H01L27/11587 ,  H10B51/10

CPC classification number: H01L27/11597 ,  H01L27/11587

Abstract: A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.

公开(公告)号：US11532343B2

公开(公告)日：2022-12-20

申请号：US17064279

申请日：2020-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chao-I Wu ,  Sheng-Chen Wang ,  Yu-Ming Lin

IPC: G11C11/22 ,  H01L27/11597 ,  H01L27/1159 ,  H01L27/11587 ,  H01L27/11582

Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

公开(公告)号：US20220230680A1

公开(公告)日：2022-07-21

申请号：US17149985

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-I Wu ,  Win-San Khwa

IPC: G11C13/00

Abstract: An integrated chip has an array of memory cells disposed over a semiconductor substrate and a driver circuit. The driver circuit provides the array with a read voltage that varies in relation to an approximate temperature of the memory array to ameliorate temperature dependencies in read currents. The driver circuit may vary the read voltage in an inverse relationship with temperature. The read voltage may be varied continuous or stepwise and the driver circuit may use a table lookup. Optionally, the driver circuit measures a current and modulates the read voltage until the current is within a target range. The memory cells may be multi-level phase change memory cells that include a plurality phase change element disposed between a bottom electrode and a top electrode. Modulating the read voltage to reduce temperature-dependent current variations is particularly useful for multi-level cells.

公开(公告)号：US20210399052A1

公开(公告)日：2021-12-23

申请号：US17123925

申请日：2020-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-I Wu ,  Yu-Ming Lin

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  G11C7/18 ,  G11C8/14 ,  H01L29/78

Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

公开(公告)号：US20210398992A1

公开(公告)日：2021-12-23

申请号：US17132305

申请日：2020-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H01L27/11502 ,  G11C5/06 ,  G11C11/22 ,  H01L27/11585

Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.