公开(公告)号：US20150034957A1

公开(公告)日：2015-02-05

申请号：US13956834

申请日：2013-08-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Han-Chin Chiu ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L21/28264 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: The present disclosure relates to an enhancement mode MISFET device. In some embodiments, the MISFET device has an electron supply layer located on top of a layer of semiconductor material. A multi-dielectric layer, having two or more stacked dielectric materials sharing an interface having negative fixed charges, is disposed above the electron supply layer. A metal gate structure is disposed above the multi-dielectric layer, such that the metal gate structure is separated from the electron supply layer by the multi-dielectric layer. The multi-dielectric layer provides fixed charges at interfaces between the separate dielectric materials, which cause the transistor device to achieve a normally off disposition.

Abstract translation: 本公开涉及增强型MISFET器件。 在一些实施例中，MISFET器件具有位于半导体材料层顶部的电子供应层。 具有两个或更多层叠电介质材料的多电介质层设置在电子供应层上方，共同具有负固定电荷的界面。 金属栅极结构设置在多电介质层上方，使得金属栅极结构通过多电介质层与电子供给层分离。 多介电层在分离的电介质材料之间的界面处提供固定的电荷，这导致晶体管器件实现常关状态。

公开(公告)号：US11522066B2

公开(公告)日：2022-12-06

申请号：US17114715

申请日：2020-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L21/02 ,  H01L23/29 ,  H01L29/20 ,  H01L23/31 ,  H01L29/78 ,  H01L29/10

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

公开(公告)号：US11038025B2

公开(公告)日：2021-06-15

申请号：US16562918

申请日：2019-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： King-Yuen Wong ,  Ming-Wei Tsai ,  Han-Chin Chiu

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/861 ,  H01L29/205

Abstract: The present disclosure, in some embodiments, relates to a method of forming a transistor device. The method may be performed by forming an anode and a cathode over an electron supply layer disposed on a semiconductor material. A doped III-N semiconductor material is formed over the electron supply layer, and an insulating material is formed over the electron supply layer and the doped III-N semiconductor material. The insulating material continuously extends from over the anode to over the cathode. The insulating material is patterned to form sidewalls of the insulating material that define an opening over the doped III-N semiconductor material. A gate structure is formed directly between the sidewalls of the insulating material and over the doped III-N semiconductor material.

公开(公告)号：US09978844B2

公开(公告)日：2018-05-22

申请号：US14583391

申请日：2014-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： King-Yuen Wong ,  Ming-Wei Tsai ,  Han-Chin Chiu

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L29/778 ,  H01L29/861

CPC classification number: H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/861

Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier (L-FER) device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A passivation layer is located over the electron supply layer and the layer of doped III-N semiconductor material. A gate structure is disposed over the layer of doped III-N semiconductor material and the passivation layer. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the passivation layer improves reliability of the L-FER device by mitigating current degradation due to high-temperature reverse bias (HTRB) stress.

公开(公告)号：US09564330B2

公开(公告)日：2017-02-07

申请号：US13956834

申请日：2013-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai

IPC: H01L29/20 ,  H01L21/28 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L21/28264 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: The present disclosure relates to an enhancement mode MISFET device. In some embodiments, the MISFET device has an electron supply layer located on top of a layer of semiconductor material. A multi-dielectric layer, having two or more stacked dielectric materials sharing an interface having negative fixed charges, is disposed above the electron supply layer. A metal gate structure is disposed above the multi-dielectric layer, such that the metal gate structure is separated from the electron supply layer by the multi-dielectric layer. The multi-dielectric layer provides fixed charges at interfaces between the separate dielectric materials, which cause the transistor device to achieve a normally off disposition.

Abstract translation: 本公开涉及增强型MISFET器件。 在一些实施例中，MISFET器件具有位于半导体材料层顶部的电子供应层。 具有两个或更多层叠电介质材料的多电介质层设置在电子供应层上方，共同具有负固定电荷的界面。 金属栅极结构设置在多电介质层上方，使得金属栅极结构通过多电介质层与电子供给层分离。 多介电层在分离的电介质材料之间的界面处提供固定的电荷，这导致晶体管器件实现常关状态。

公开(公告)号：US09449867B2

公开(公告)日：2016-09-20

申请号：US14306643

申请日：2014-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Heng Wu ,  Yi-Hsien Chang ,  Kai-Chih Liang ,  Yi Heng Tsai ,  Wei-Cheng Shen ,  Chun-Ren Cheng ,  Chun-Wen Cheng ,  Han-Chin Chiu

IPC: B81C3/00 ,  B81B7/00 ,  H01L21/762 ,  H01L23/00 ,  H01L27/092

CPC classification number: H01L21/76232 ,  B81B7/0025 ,  B81B7/0054 ,  B81B7/008 ,  B81C1/00238 ,  B81C1/00801 ,  B81C3/001 ,  H01L24/89 ,  H01L27/092

Abstract: The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.

Abstract translation: 本公开涉及具有保护屏障结构的集成微系统以及相关联的方法。 在一些实施例中，集成微系统包括具有设置在其上的多个CMOS器件的第一管芯，具有设置在其上的多个MEMS器件的第二管芯和设置在第一管芯和第二管芯之间的蒸气氢氟酸（vHF） 死。 第二管芯在接合界面区域与第一管芯接合。 vHF蚀刻阻挡结构包括位于第一管芯的上表面上方的vHF阻挡层，以及布置在第一管芯的上表面之间的应力减小层。

公开(公告)号：US20150364363A1

公开(公告)日：2015-12-17

申请号：US14306643

申请日：2014-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Heng Wu ,  Yi-Hsien Chang ,  Kai-Chih Liang ,  Yi Heng Tsai ,  Wei-Cheng Shen ,  Chun-Ren Cheng ,  Chun-Wen Cheng ,  Han-Chin Chiu

IPC: H01L21/762 ,  B81C3/00 ,  B81B7/00 ,  H01L27/092 ,  H01L23/00

CPC classification number: H01L21/76232 ,  B81B7/0025 ,  B81B7/0054 ,  B81B7/008 ,  B81C1/00238 ,  B81C1/00801 ,  B81C3/001 ,  H01L24/89 ,  H01L27/092

Abstract: The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.

Abstract translation: 本公开涉及具有保护屏障结构的集成微系统以及相关联的方法。 在一些实施例中，集成微系统包括具有设置在其上的多个CMOS器件的第一管芯，具有设置在其上的多个MEMS器件的第二管芯和设置在第一管芯和第二管芯之间的蒸气氢氟酸（vHF） 死。 第二管芯在接合界面区域与第一管芯接合。 vHF蚀刻阻挡结构包括位于第一管芯的上表面上方的vHF阻挡层，以及布置在第一管芯的上表面之间的应力减小层。

公开(公告)号：US11594606B2

公开(公告)日：2023-02-28

申请号：US17166775

申请日：2021-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chen-Hao Chiang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

公开(公告)号：US20210184011A1

公开(公告)日：2021-06-17

申请号：US17166775

申请日：2021-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chen-Hao Chiang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

公开(公告)号：US10991803B2

公开(公告)日：2021-04-27

申请号：US15959459

申请日：2018-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： King-Yuen Wong ,  Ming-Wei Tsai ,  Han-Chin Chiu

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/861 ,  H01L29/205

Abstract: The present disclosure, in some embodiments relates to a semiconductor device. The semiconductor device includes a layer of semiconductor material disposed over a substrate and an electron supply layer disposed over the layer of semiconductor material between an anode terminal and a cathode terminal. A layer of III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer contacts an upper surface of the electron supply layer and further contacts an upper surface and a sidewall of the layer of III-N semiconductor material. A gate structure is separated from the layer of III-N semiconductor material by the passivation layer.