公开(公告)号：US11522066B2

公开(公告)日：2022-12-06

申请号：US17114715

申请日：2020-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L21/02 ,  H01L23/29 ,  H01L29/20 ,  H01L23/31 ,  H01L29/78 ,  H01L29/10

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

公开(公告)号：US11515408B2

公开(公告)日：2022-11-29

申请号：US16806108

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuei-Ming Chen ,  Chi-Ming Chen ,  Chung-Yi Yu

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/02

Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

公开(公告)号：US20210391435A1

公开(公告)日：2021-12-16

申请号：US16901512

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Kuei-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/78

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

公开(公告)号：US20210273084A1

公开(公告)日：2021-09-02

申请号：US16806108

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuei-Ming Chen ,  Chi-Ming Chen ,  Chung-Yi Yu

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02

Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

公开(公告)号：US20190013399A1

公开(公告)日：2019-01-10

申请号：US16132793

申请日：2018-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/43 ,  H01L29/201

Abstract: The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlzGa(1-z)N is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlxGa(1-x)N is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlzGa(1-z)N. A gate structure is laterally between the source and drain contacts.

公开(公告)号：US20160322225A1

公开(公告)日：2016-11-03

申请号：US14699046

申请日：2015-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Po-Chun Liu

IPC: H01L21/02 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L21/02694 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02617 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: The present disclosure relates to a structure and method of forming a GaN film on a Si substrate that includes an additional or second high temperature (HT) AlN seed layer, introduced for reducing the tensile stress of GaN on a Si substrate. The second HT AlN seed layer is disposed over a first HT AlN seed layer, and has a low V/III ratio compared to the first HT AlN seed layer. The second HT AlN seed layer has better lattice matching between Si and GaN and this reduces the tensile stress on GaN. The additional HT AlN seed layer further acts as a capping layer and helps annihilate or terminate threading dislocations (TDs) originating from a LT AlN seed layer. The second HT AlN seed layer also helps prevent Si diffusion from the substrate to the GaN film.

Abstract translation: 本公开内容涉及在Si衬底上形成GaN膜的结构和方法，该衬底包括用于降低Si衬底上GaN的拉伸应力的额外的或第二高温（HT）AlN晶种层。 第二HT AlN种子层设置在第一HT AlN籽晶层上，并且与第一HT AlN种子层相比具有低的V / III比。 第二个HT AlN种子层在Si和GaN之间具有更好的晶格匹配，并且这降低了GaN上的拉伸应力。 附加的HT AlN种子层还起到盖层的作用，并有助于消除或终止来自LT AlN种子层的穿透位错（TD）。 第二HT AlN种子层还有助于防止Si从衬底扩散到GaN膜。

公开(公告)号：US11984486B2

公开(公告)日：2024-05-14

申请号：US18158192

申请日：2023-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chen-Hao Chiang

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/42364 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/2003

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

公开(公告)号：US11824099B2

公开(公告)日：2023-11-21

申请号：US16901512

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Kuei-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L29/42384 ,  H01L29/785 ,  H01L29/7889

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

公开(公告)号：US20200098889A1

公开(公告)日：2020-03-26

申请号：US16695392

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L21/02 ,  H01L23/29 ,  H01L29/20 ,  H01L23/31 ,  H01L29/78

Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.

公开(公告)号：US10522647B2

公开(公告)日：2019-12-31

申请号：US16010641

申请日：2018-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/778 ,  H01L29/205 ,  H01L23/31 ,  H01L23/29 ,  H01L29/20 ,  H01L29/10

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer. Source and drain regions are arranged over the second III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.