公开(公告)号：US11018057B2

公开(公告)日：2021-05-25

申请号：US16876127

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Hsiang Su ,  Jyh-Huei Chen ,  Kuo-Chiang Tsai ,  Ke-Jing Yu

IPC: H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/033 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on a top surface of the first gate structure, a second hard mask on the second gate structure and a third hard mask disposed between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask. A bottom surface of the third hard mask is substantially flush with a bottom surface of the first gate structure.

公开(公告)号：US10950729B2

公开(公告)日：2021-03-16

申请号：US16171763

申请日：2018-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/02 ,  H01L23/522

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering an upper surface of the gate stack, a second insulating capping feature covering an upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from a material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.

公开(公告)号：US10825721B2

公开(公告)日：2020-11-03

申请号：US16180913

申请日：2018-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Ke-Jing Yu ,  Jyh-Huei Chen

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure laterally adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering the upper surface of the gate stack, a second insulating capping feature covering the upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from the material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.

公开(公告)号：US20200168502A1

公开(公告)日：2020-05-28

申请号：US16371780

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/522

Abstract: In one example, a method includes performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of an underlying feature, performing a third etching process to laterally recess the etch stop layer, and depositing a conductive material over the underlying feature to create a conductive feature in direct contact with the underlying feature.

公开(公告)号：US20140252468A1

公开(公告)日：2014-09-11

申请号：US13788524

申请日：2013-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Wei-Yuan Lu ,  Lilly Su ,  Chun-Hung Huang ,  Chii-Horng Li ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/823418 ,  H01L29/0843 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66053 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66689 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects.

Abstract translation: 具有场效应晶体管的集成电路器件具有包括第一和第二层的源区和漏区。 第一层形成在通道区域的平面之下。 第一层包括具有小于硅的晶格结构的掺杂硅和碳。 第二层形成在第一层上并且在沟道区的平面上方上升。 第二层由包括掺杂的外延生长的硅的材料形成。 第二层的碳原子分数小于第一层的一半。 第一层形成在通道区域的表面下方至少10nm的深度。 该结构有助于形成非常浅的结的源极和漏极扩展区域。 这些装置提供具有低电阻的源和漏极，同时抵抗短沟道效应。

公开(公告)号：US12154957B2

公开(公告)日：2024-11-26

申请号：US17379265

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L29/417 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.

公开(公告)号：US11545432B2

公开(公告)日：2023-01-03

申请号：US17083976

申请日：2020-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768

Abstract: An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.

公开(公告)号：US20220359393A1

公开(公告)日：2022-11-10

申请号：US17873782

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L21/768 ,  H01L27/02

Abstract: A method includes receiving a semiconductor structure having a source contact feature electrically connected to a source feature and a drain contact feature electrically connected to a drain feature. The method includes etching to form a drain via trench over the drain contact feature and forming a drain via in the drain via trench. After forming the drain via, the method further includes etching to form a source via trench over the source contact feature and forming a source via in the source via trench. The drain via has a first dimension along a first direction, the source via has a second dimension along the first direction, and the second dimension is greater than the first dimension.

公开(公告)号：US20210272901A1

公开(公告)日：2021-09-02

申请号：US17083976

申请日：2020-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/8234

Abstract: An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.

公开(公告)号：US20200043787A1

公开(公告)日：2020-02-06

申请号：US16175802

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Hsiang Su ,  Jyh-Huei Chen ,  Kuo-Chiang Tsai ,  Ke-Jing Yu

IPC: H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/033

Abstract: Semiconductor devices are provided, and includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on the first gate structure and a second hard mask on the second gate structure and a third hard mask. The third hard mask is disposed in a dielectric layer between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask.