公开(公告)号：US20230147413A1

公开(公告)日：2023-05-11

申请号：US18149265

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Kuo-Chiang Tsai ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0207 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/0847

Abstract: A semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device includes a source via electrically coupled to the source feature and a drain via electrically coupled to the drain feature. The semiconductor device includes a source via metal line disposed over and directly connected to the source via. The semiconductor device includes and a drain via metal line disposed over and directly connected to the drain via. The source via metal line has two first outer edges extending lengthwise along a first direction and at least one of the first outer edges is substantially aligned with an edge of the source via from a top view. The drain via metal line has two second outer edges extending lengthwise along the first direction and the two second outer edges are offset from edges of the drain via from a top view.

公开(公告)号：US11569362B2

公开(公告)日：2023-01-31

申请号：US16927953

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ming Hsu ,  Pei-Yu Chou ,  Chih-Pin Tsao ,  Kuang-Yuan Hsu ,  Jyh-Huei Chen

IPC: H01L29/66 ,  H01L29/45 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/285 ,  H01L29/78 ,  H01L21/02

Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

公开(公告)号：US11081585B2

公开(公告)日：2021-08-03

申请号：US16907781

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Ke-Jing Yu ,  Chih-Hong Hwang ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.

公开(公告)号：US10950497B2

公开(公告)日：2021-03-16

申请号：US16371780

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/522 ,  H01L21/321 ,  H01L21/027

Abstract: In one example, a method includes performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of an underlying feature, performing a third etching process to laterally recess the etch stop layer, and depositing a conductive material over the underlying feature to create a conductive feature in direct contact with the underlying feature.

公开(公告)号：US10658237B2

公开(公告)日：2020-05-19

申请号：US16175802

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Hsiang Su ,  Jyh-Huei Chen ,  Kuo-Chiang Tsai ,  Ke-Jing Yu

IPC: H01L29/06 ,  H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/033 ,  H01L21/8238

Abstract: Semiconductor devices are provided, and includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on the first gate structure and a second hard mask on the second gate structure and a third hard mask. The third hard mask is disposed in a dielectric layer between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask.

公开(公告)号：US11955380B2

公开(公告)日：2024-04-09

申请号：US18057158

申请日：2022-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L21/027 ,  H01L21/321

CPC classification number: H01L21/76877 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32133 ,  H01L23/5226 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684

Abstract: In one example, a semiconductor device includes a first conductive feature embedded in a first dielectric layer such that a top surface of the first dielectric layer is higher than a top surface of first conductive feature, a contact etch stop layer (CESL) disposed on the first dielectric layer, and a second conductive feature embedded in a second dielectric layer. The second dielectric layer is disposed on the CESL and the second conductive feature extends through the CESL and is in direct contact with the first conductive feature.

公开(公告)号：US11139203B2

公开(公告)日：2021-10-05

申请号：US16263143

申请日：2019-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Ke-Jing Yu ,  Fu-Hsiang Su ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L21/308 ,  H01L21/311

Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.

公开(公告)号：US11011636B2

公开(公告)日：2021-05-18

申请号：US16199551

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Han Wu ,  Yu-Ho Chiang ,  Jyh-Huei Chen ,  Jhon-Jhy Liaw

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate, and forming a source/drain (S/D) structure over the fin structure. The method for forming a FinFET device structure also includes forming an inter-layer dielectric (ILD) structure covering the S/D structure, and forming a gate structure over the fin structure and adjacent to the S/D structure. The method for forming a FinFET device structure further includes forming a first hard mask layer over the gate structure, and forming a second hard mask layer over the first hard mask layer. In addition, the method for forming a FinFET device structure includes etching the ILD structure to form an opening exposing the S/D structure. The opening and a recess in the second hard mask layer are formed simultaneously.

公开(公告)号：US20200279774A1

公开(公告)日：2020-09-03

申请号：US16876127

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Hsiang Su ,  Jyh-Huei Chen ,  Kuo-Chiang Tsai ,  Ke-Jing Yu

IPC: H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/033 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on a top surface of the first gate structure, a second hard mask on the second gate structure and a third hard mask disposed between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask. A bottom surface of the third hard mask is substantially flush with a bottom surface of the first gate structure.

公开(公告)号：US20190051542A1

公开(公告)日：2019-02-14

申请号：US16155186

申请日：2018-10-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Jung LIU ,  Chih-Pin Tsao ,  Chia-Wei Soong ,  Jyh-Huei Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC: H01L21/67 ,  H01L29/78 ,  H01L23/485 ,  H01L21/311 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/027

Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent. An example benefit includes reduction or elimination of diffusion of fluorine contaminants from a gate metal fill layer into its underlying layers and from conductive layers into diffusion barrier layers and silicide layers of source/drain contact structures and consequently, the reduction of the negative impact of these fluorine contaminants on device performance.