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    FIELD EFFECT TRANSISTOR WITH GATE ISOLATION STRUCTURE AND METHOD
    22.
    发明申请
    FIELD EFFECT TRANSISTOR WITH GATE ISOLATION STRUCTURE AND METHOD 有权

    公开(公告)号：US20230014998A1

    公开(公告)日：2023-01-19

    申请号：US17379936

    申请日：2021-07-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Kuan-Lun CHENG ,  Guan-Lin CHEN ,  Kuan-Ting PAN

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

    Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

    SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME
    24.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME 有权

    公开(公告)号：US20220302280A1

    公开(公告)日：2022-09-22

    申请号：US17806100

    申请日：2022-06-09

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chi-Yi CHUANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

    IPC: H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

    Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-κ gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.

    SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
    27.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20220093595A1

    公开(公告)日：2022-03-24

    申请号：US17027322

    申请日：2020-09-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Yi-Ruei JHAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

    IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.

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