公开(公告)号：US20190139777A1

公开(公告)日：2019-05-09

申请号：US16221766

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Wen-Ting LAN ,  Shi-Ning JU ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method includes forming a mandrel structure over a semiconductor substrate. A first spacer and a second spacer are formed alongside the mandrel structure. A mask layer is over a first portion of the first spacer, in which a second portion of the first spacer and the second spacer are exposed from the mask layer. The exposed second spacer is etched, in which etching the exposed second spacer is performed such that a polymer is formed over a top surface of the exposed second portion of the first spacer. The mask layer, the polymer, and the mandrel structure are removed. The semiconductor substrate is patterned using the first spacer.

公开(公告)号：US20230142902A1

公开(公告)日：2023-05-11

申请号：US17750239

申请日：2022-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning JU ,  Wen-Ting LAN ,  I-Han HUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L24/98 ,  H01L2924/35121 ,  H01L2224/08225 ,  H01L2224/80006 ,  H01L2224/80896

Abstract: A method of manufacturing a semiconductor device structure includes bonding a device substrate to a first de-bond layer. The first de-bond layer is disposed on a first carrier substrate, and the device substrate has a first side facing the first carrier substrate and a second side opposite from the first side. The device substrate has a first width. A front-end-of-line (FEOL) process and a back-end-of-line (BEOL) process are performed on the device substrate. A second carrier substrate having a second de-bond layer is bonded on the second side of the device substrate. The first carrier substrate is removed by removing the first de-bond layer. A width of the device substrate remains the first width after removing the first carrier substrate.

公开(公告)号：US20210159311A1

公开(公告)日：2021-05-27

申请号：US16697647

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting LAN ,  Guan-Lin CHEN ,  Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Semiconductor structures and method for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a first fin structure including first semiconductor material layers and second semiconductor material layers alternately stacked over a substrate and forming an isolation structure surrounding the first fin structure. The method for manufacturing the semiconductor structure also includes forming a first capping layer over the isolation structure and covering a top surface and sidewalls of the first fin structure and etching the isolation structure to form a first gap between the first capping layer and a top surface of the isolation structure. The method for manufacturing the semiconductor structure also includes forming a protection layer covering a sidewall of the first capping layer and filling in the first gap.

公开(公告)号：US20210111262A1

公开(公告)日：2021-04-15

申请号：US17106933

申请日：2020-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao WANG ,  Shi-Ning JU ,  Kai-Chieh YANG ,  Wen-Ting LAN ,  Wai-Yi LIEN

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/8234

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

公开(公告)号：US20170358654A1

公开(公告)日：2017-12-14

申请号：US15665276

申请日：2017-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao WANG ,  Wai-Yi LIEN ,  Shi-Ning JU ,  Kai-Chieh YANG ,  Wen-Ting LAN

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/7827

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.