公开(公告)号：US09129988B1

公开(公告)日：2015-09-08

申请号：US14555439

申请日：2014-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lee ,  Ting-Yeh Chen ,  Chia-Ling Chan ,  Chien-Tai Chan

IPC: H01L21/00 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET includes a fin structure, a gate and a source-drain region. The fin structure is over a substrate and has a recess of an upper surface of the fin structure and a doped region in the fin structure and adjacent to the recess. The gate protrudes from the recess and across over the fin structure. The source-drain region is in the fin structure and adjacent to the doped region. Methods for forming the FinFET are also provided.

Abstract translation: FinFET包括鳍结构，栅极和源极 - 漏极区域。 翅片结构在衬底之上，并且具有翅片结构的上表面的凹部和鳍结构中的与凹部相邻的掺杂区域。 门从凹槽突出并跨过翅片结构。 源极 - 漏极区域处于鳍状结构并且与掺杂区域相邻。 还提供了形成FinFET的方法。

公开(公告)号：US12154947B2

公开(公告)日：2024-11-26

申请号：US17705540

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.

公开(公告)号：US20220285513A1

公开(公告)日：2022-09-08

申请号：US17465665

申请日：2021-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Da-Wen Lin

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

公开(公告)号：US20220181469A1

公开(公告)日：2022-06-09

申请号：US17651839

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/8238

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

公开(公告)号：US11289574B2

公开(公告)日：2022-03-29

申请号：US16727766

申请日：2019-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.

公开(公告)号：US20210296498A1

公开(公告)日：2021-09-23

申请号：US17341088

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/11 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/165 ,  H01L21/84 ,  H01L29/08 ,  H01L27/092

Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins with a first gate pitch and second gate structures engaging the second fins with a second gate pitch smaller than the first gate pitch. The semiconductor structure also includes first epitaxial semiconductor features partially embedded in the first fins and adjacent the first gate structures and second epitaxial semiconductor features partially embedded in the second fins and adjacent the second gate structures. A bottom surface of the first epitaxial semiconductor features is lower than a bottom surface of the second epitaxial semiconductor features.

公开(公告)号：US11011634B2

公开(公告)日：2021-05-18

申请号：US15431144

申请日：2017-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lee ,  Ting-Yeh Chen ,  Chii-Horng Li ,  Feng-Cheng Yang

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165 ,  H01L29/08 ,  H01L21/8238

Abstract: A semiconductor device includes a semiconductor substrate, an n-type fin field effect transistor. The n-type fin field effect transistor includes a fin structure, a gate stack, and a source/drain region. The gate stack includes a gate dielectric and a gate electrode. The gate dielectric is disposed in between the fin structure and the gate electrode. The source/drain region includes an epitaxial structure and an epitaxy coat covering the epitaxial structure. The epitaxial structure is made of a material having a lattice constant larger than a channel region. The epitaxy coat is made of a material having a lattice constant lower than the channel region.

公开(公告)号：US20190123200A1

公开(公告)日：2019-04-25

申请号：US16217150

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/161 ,  H01L27/11 ,  H01L29/08 ,  H01L21/84 ,  H01L29/165 ,  H01L29/66 ,  H01L29/16

Abstract: A semiconductor structure includes a first region. The first region includes at least three first gate structures separate one from another and adjacent to each other and at least three second gate structures separate one from another and adjacent to each other. The first gate structures are further away from each other than the second gate structures. The first region further includes first epitaxial semiconductor features proximate the first gate structures and second epitaxial semiconductor features proximate the second gate structures. A first distance from the first epitaxial semiconductor features to the respective first gate structures is smaller than a second distance from the second epitaxial semiconductor features to the respective second gate structures.

公开(公告)号：US10158007B2

公开(公告)日：2018-12-18

申请号：US15725040

申请日：2017-10-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lee ,  Feng-Cheng Yang ,  Ting-Yeh Chen

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure. The first fin structure and the second fin structure are both disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction in plan view. A first void is formed in the source/drain structure.

公开(公告)号：US20180151731A1

公开(公告)日：2018-05-31

申请号：US15431144

申请日：2017-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lee ,  Ting-Yeh Chen ,  Chii-Horng Li ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

Abstract: A semiconductor device includes a semiconductor substrate, an n-type fin field effect transistor. The n-type fin field effect transistor includes a fin structure, a gate stack, and a source/drain region. The gate stack includes a gate dielectric and a gate electrode. The gate dielectric is disposed in between the fin structure and the gate electrode. The source/drain region includes an epitaxial structure and an epitaxy coat covering the epitaxial structure. The epitaxial structure is made of a material having a lattice constant larger than a channel region. The epitaxy coat is made of a material having a lattice constant lower than the channel region.