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21.发明授权
公开(公告)号：US5821591A
公开(公告)日：1998-10-13
申请号：US794566
申请日：1997-02-03
IPC分类号： H01L21/8246 , H01L27/112 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/1128 , H01L27/112
摘要： A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed on the side walls of the trenches. The memory cell configuration can be produced with a mean area requirement for each memory cell of 1 F.sup.2, where F is the minimum structure size.
摘要翻译： 存储单元配置包括具有平面MOS晶体管的第一存储单元和具有垂直MOS晶体管的第二存储单元。 平面MOS晶体管设置在平行的带状沟槽的底部和顶部上。 垂直MOS晶体管设置在沟槽的侧壁上。 存储单元配置可以用1 F2的每个存储单元的平均面积要求来生成，其中F是最小结构尺寸。
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22.发明授权Electrically programmable memory cell array, using charge carrier traps and insulation trenches 失效电可编程存储单元阵列，使用电荷载流子阱和绝缘沟槽公开(公告)号：US06191459B1
公开(公告)日：2001-02-20
申请号：US08780488
申请日：1997-01-08
IPC分类号： H01L2976
CPC分类号： H01L29/7926 , H01L27/115 , H01L27/11556 , H01L29/792
摘要： An electrically programmable memory cell array is formed of memory cells, which include a vertical MOS transistor. The MOS transistor has a gate dielectric of a material with charge carrier traps. The memory cells are disposed along opposite edges of striplike, parallel insulation trenches. The width and spacing of the insulation trenches are preferably identical. The space required per memory cell of the memory cell array is 2F2, where F is the minimum structural size in the technology employed. The memory cells are programmed by selectively injecting electrons into the gate dielectric.
摘要翻译： 电可编程存储单元阵列由包括垂直MOS晶体管的存储单元形成。 MOS晶体管具有具有电荷载流子阱的材料的栅极电介质。 存储单元沿带状平行绝缘沟槽的相对边缘设置。 绝缘沟槽的宽度和间距优选相同。 存储单元阵列每个存储单元所需的空间为2F2，其中F为所采用技术中的最小结构尺寸。 通过选择性地将电子注入到栅极电介质中来对存储器单元进行编程。
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23.发明授权Memory cell arrangement with vertical MOS transistors and the production process thereof 失效具有垂直MOS晶体管的存储单元布置及其制造工艺公开(公告)号：US06180979B2
公开(公告)日：2001-01-30
申请号：US09142462
申请日：1998-09-08
IPC分类号： H01L2972
CPC分类号： H01L27/11273 , H01L27/112
摘要： In a memory cell arrangement which has vertical MOS transistors as memory cells, the information is stored by different threshold voltages of the transistors. For this purpose, dopant regions are formed for an information state by angled implantation or outdiffusion in the upper region of the channel region. The lower region of the channel region is in this case covered by an etching residue (9′) which is formed by masked spacer etching. The arrangement can be produced with an area requirement for each memory cell of 2 F2 (F: minimum structure size).
摘要翻译： 在具有作为存储单元的垂直MOS晶体管的存储单元布置中，通过晶体管的不同阈值电压来存储信息。 为此，通过在通道区域的上部区域中的成角度注入或扩散扩散来形成信息状态的掺杂剂区域。 在这种情况下，沟道区域的下部区域由被掩模的间隔物蚀刻形成的蚀刻残留物（9'）覆盖。 可以按照2 F2（F：最小结构尺寸）的每个存储单元的面积要求来生成该布置。
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公开(公告)号：US6153475A
公开(公告)日：2000-11-28
申请号：US331495
申请日：1999-06-21
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Wolfgang Krautschneider , Paul-Werner von Basse
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Wolfgang Krautschneider , Paul-Werner von Basse
IPC分类号： H01L21/8246 , H01L27/112 , H01L21/336
CPC分类号： H01L27/112
摘要： For the manufacture of a memory cell arrangement with first memory cells that comprise a vertical MOS transistor and with second memory cells that do not comprise an MOS transistor, whereby the memory cells are arranged along opposite edges of strip-type trenches, memory cells that are adjacent along the trenches (5) are manufactured successively. The spacing of adjacent memory cells is determined in particular by means of a spacer technology. By this means, a space requirement per memory cell of 1F.sup.2 can be realized, whereby F is the minimum structural size of the respective technology.
摘要翻译： PCT No.PCT / DE97 / 02549 Sec。 371 1999年6月21日第 102（e）日期1999年6月21日PCT 1997年11月4日PCT PCT。 第WO98 / 27586号公报 日期1998年6月25日为了制造具有包括垂直MOS晶体管的第一存储单元和不包括MOS晶体管的第二存储单元的存储单元布置，由此存储单元沿带状沟槽的相对边缘布置 沿着沟槽（5）相邻的存储单元依次制造。 特别是通过间隔物技术来确定相邻存储单元的间隔。 通过这种方式，可以实现1F2的每个存储单元的空间要求，由此F是相应技术的最小结构尺寸。
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25.发明授权DRAM cell arrangement having dynamic self-amplifying memory cells, and method for manufacturing same 失效具有动态自放大存储单元的DRAM单元布置及其制造方法
公开(公告)号：US6049105A
公开(公告)日：2000-04-11
申请号：US89539
申请日：1998-06-03
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/108 , H01L27/10876
摘要： A DRAM cell arrangement having dynamic, self-amplifying memory cells, and method for manufacturing same, wherein each memory cell includes a selection transistor, a memory transistor and a diode structure. The selection transistor and the memory transistor are each fashioned as vertical MOS transistors and are arranged one over the other such that they are connected to one another via a common source/drain region. A source/drain region of the memory transistor is connected to a supply voltage line, a source/drain region of the selection transistor is connected to a bitline, and the gate electrode of the selection transistor is connected to a wordline. A diode structure is connected between the common source/drain region and the gate electrode of the memory transistor.
摘要翻译： 具有动态，自放大存储单元的DRAM单元布置及其制造方法，其中每个存储单元包括选择晶体管，存储晶体管和二极管结构。 选择晶体管和存储晶体管各自被形成为垂直MOS晶体管，并且彼此重叠地布置成使得它们经由公共源极/漏极区彼此连接。 存储晶体管的源极/漏极区域连接到电源电压线，选择晶体管的源极/漏极区域连接到位线，并且选择晶体管的栅极电极连接到字线。 在公共源极/漏极区域和存储晶体管的栅电极之间连接二极管结构。
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公开(公告)号：US5998261A
公开(公告)日：1999-12-07
申请号：US973701
申请日：1997-12-08
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11517 , H01L27/115
摘要： An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.
摘要翻译： PCT No.PCT / DE96 / 01117 Sec。 371 1997年12月8日第 102（e）日期1997年12月8日PCT提交1996年6月25日PCT公布。 第WO97 / 02599号公报 日期1997年1月23日在半导体衬底（优选单晶硅）或SOI衬底的硅层中制造的电可写和可擦除的只读存储单元布置。 具有存储单元的单元阵列设置在半导体基板的主表面上。 每个存储单元包括垂直于主表面的MOS晶体管，并且除了源极/漏极区域和布置在其之间的沟道区域之外还包括第一电介质，浮动栅极，第二电介质和控制栅极。 多个基本上平行的带状沟槽设置在单元阵列中。 垂直MOS晶体管布置在沟槽的侧面。 存储单元在每种情况下都布置在沟槽的相对侧面上。
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公开(公告)号：US5994746A
公开(公告)日：1999-11-30
申请号：US232083
申请日：1999-01-15
IPC分类号： G11C17/08 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115
CPC分类号： H01L27/11273 , H01L27/112
摘要： The memory cell has transistors that are arranged three-dimensionally. Vertical MOS transistors are arranged on the sidewalls of semiconductor webs, and a plurality of transistors are arranged one above the other on each sidewall. The transistors that are arranged one above the other on a sidewall are connected in series.
摘要翻译： 存储单元具有三维布置的晶体管。 垂直MOS晶体管布置在半导体薄片的侧壁上，并且多个晶体管彼此并排设置在每个侧壁上。 在侧壁上一个上下配置的晶体管串联连接。
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公开(公告)号：US5920099A
公开(公告)日：1999-07-06
申请号：US913332
申请日：1997-09-11
IPC分类号： H01L21/8246 , H01L27/112
CPC分类号： H01L27/1126 , H01L27/112
摘要： A read-only memory cell array has a plurality of individual memory cells which each have a MOS transistor and which are arranged in rows running in parallel. In this context, adjacent rows run alternately at the bottom of the longitudinal trenches (6) and between adjacent longitudinal trenches (6) respectively and are insulated with respect to one another. The read-only memory cell array can be manufactured by self-aligning process steps with an area of 2 F.sup.2 (F: minimum structure size) being required per memory cell.
摘要翻译： PCT No.PCT / DE96 / 00380 Sec。 371日期：1997年9月11日 102（e）1997年9月11日PCT PCT 1996年3月4日PCT公布。 公开号WO96 / 29739 日期1996年9月26日只读存储单元阵列具有多个单独的存储单元，每个单独存储单元具有MOS晶体管并且并行排列。 在这种情况下，相邻的行分别在纵向沟槽（6）的底部和相邻的纵向沟槽（6）之间交替地延伸并相对于彼此绝缘。 只读存储单元阵列可以通过每个存储单元需要2 F2（F：最小结构尺寸）面积的自对准工艺步骤来制造。
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29.发明授权Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells 失效包含自放大动态MOS晶体管存储单元的制造和布置方法
公开(公告)号：US5710072A
公开(公告)日：1998-01-20
申请号：US737236
申请日：1996-11-18
IPC分类号： H01L27/08 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L21/336
CPC分类号： H01L27/10844 , H01L27/0629 , H01L27/108
摘要： To produce an arrangement containing self-amplifying dynamic MOS transistor memory cells which each comprise a selection transistor, a memory transistor and a diode structure, the selection transistor and the memory transistor being connected in series via a common nodal point and the diode structure being connected between the common nodal point and the gate electrode (10) of the memory transistor, the selection transistor and the memory transistor are formed as vertical MOS transistors. For this purpose a vertical sequence of suitably doped zones (2, 3, 4) in which trenches (5, 6) are produced and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is produced, in particular, by LPCVD epitaxy or by molecular-beam epitaxy.
摘要翻译： PCT No.PCT / EP95 / 01656 Sec。 371日期：1996年11月18日 102（e）1996年11月18日PCT PCT 1995年5月2日PCT公布。 公开号WO95 / 31828 日期：1995年11月23日为了制造包含自放大动态MOS晶体管存储单元的布置，每个包括选择晶体管，存储晶体管和二极管结构，选择晶体管和存储晶体管通过公共节点串联连接， 二极管结构连接在存储晶体管的公共节点和栅电极（10）之间，选择晶体管和存储晶体管形成为垂直MOS晶体管。 为此，产生其中产生沟槽（5,6）并且设置有栅极电介质（7,8）和栅电极（9,10））的适当掺杂区（2,3,4）的垂直序列， 特别是通过LPCVD外延或通过分子束外延。
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公开(公告)号：US06180458B2
公开(公告)日：2001-01-30
申请号：US09095260
申请日：1998-06-10
IPC分类号： H01L21336
CPC分类号： H01L27/1128 , H01L27/112
摘要： A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed on the side walls of the trenches. The memory cell configuration can be produced with a mean area requirement for each memory cell of 1 F2, where F is the minimum structure size.
摘要翻译： 存储单元配置包括具有平面MOS晶体管的第一存储单元和具有垂直MOS晶体管的第二存储单元。 平面MOS晶体管设置在平行的带状沟槽的底部和顶部上。 垂直MOS晶体管设置在沟槽的侧壁上。 存储单元配置可以用1 F2的每个存储单元的平均面积要求来生成，其中F是最小结构尺寸。
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