公开(公告)号：US07080349B1

公开(公告)日：2006-07-18

申请号：US10818029

申请日：2004-04-05

申请人： Carl Babcock ,  Luigi Capodieci

发明人： Carl Babcock ,  Luigi Capodieci

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/68 ,  G06F2217/12 ,  Y02P90/265

摘要： A method for developing an optimized layout fragmentation script for an optical proximity correction (OPC) simulation tool. A test pattern layout having at least one structure representing a portion of the integrated circuit layout is provided. Optical proximity correction is iteratively conducted on the test pattern layout for each desired permutation of at least one fragmentation parameter associated with the test pattern layout and, for each permutation, a corrected test pattern layout is generated. A printed simulation of each corrected test pattern layout is made and analyzed to select one of the permutations of the at least one fragmentation parameter to apply to a integrated circuit layout prior to correction with the OPC simulation tool.

摘要翻译： 一种用于开发光学邻近校正（OPC）仿真工具的优化布局分片脚本的方法。 提供了具有表示集成电路布局的一部分的至少一个结构的测试图案布局。 对于与测试图案布局相关联的至少一个碎片参数的每个期望排列，对测试图案布局迭代地进行光学邻近校正，并且对于每个排列，生成校正的测试图案布局。 对每个校正的测试图案布局的印刷模拟进行分析，以便在使用OPC模拟工具进行校正之前选择至少一个碎片参数的一个排列以应用于集成电路布局。

公开(公告)号：US6115108A

公开(公告)日：2000-09-05

申请号：US205897

申请日：1998-12-04

申请人： Luigi Capodieci

发明人： Luigi Capodieci

IPC分类号： G03F7/20 ,  G03B27/32

CPC分类号： G03F7/70491 ,  G03F7/70125 ,  G03F7/705 ,  G03F7/70591 ,  G03F7/70625

摘要： A method (400) of determining a custom illumination scheme for a projection-type photolithography system (500) is disclosed. The custom illumination scheme provides compensation for imaging system aberrations within the photolithography system (500) and thereby reduces critical dimension non-uniformities of features produced by the photolithography system (500) across a substrate (120). The method (400) includes the steps of performing a lithography simulation (404) for one or more nominal features using imaging system aberration data which characterizes the photolithography system (500) and an initial illumination scheme. The lithography simulation includes one or more simulated features which differ from the one or more nominal features due to the imaging system aberration data. The method (400) further includes determining whether the difference between the one or more nominal features and the one or more simulated features is less than an acceptable threshold (408) and varying the illumination scheme (412) to thereby form a modified illumination scheme if the difference is not less than the acceptable threshold. Another lithography simulation is then performed (404) for the one or more nominal features using the imaging system aberration data and the modified illumination scheme, and the above steps are repeated until the difference is less than the acceptable threshold (410).

摘要翻译： 公开了一种确定投影型光刻系统（500）的定制照明方案的方法（400）。 定制照明方案为光刻系统（500）内的成像系统像差提供补偿，从而降低由光刻系统（500）跨越衬底（120）产生的特征的临界尺寸不均匀性。 方法（400）包括以下步骤：使用表征光刻系统（500）的成像系统像差数据和初始照明方案，对一个或多个标称特征进行光刻模拟（404）。 光刻模拟包括由于成像系统像差数据而与一个或多个标称特征不同的一个或多个模拟特征。 方法（400）还包括确定一个或多个标称特征与一个或多个模拟特征之间的差是否小于可接受阈值（408）并改变照明方案（412），从而形成修改照明方案，如果 差异不小于可接受的阈值。 然后使用成像系统像差数据和修改的照明方案对一个或多个标称特征执行另一光刻模拟（404），并且重复上述步骤直到差值小于可接受阈值（410）。

公开(公告)号：US08924896B2

公开(公告)日：2014-12-30

申请号：US13755374

申请日：2013-01-31

申请人： Lynn Wang ,  Vito Dai ,  Luigi Capodieci

发明人： Lynn Wang ,  Vito Dai ,  Luigi Capodieci

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F17/5081 ,  Y02T10/82

摘要： A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

摘要翻译： 提供了一种用于基于自动图案的半导体设计布局校正的工艺和装置。 实施例包括扫描绘制的半导体设计布局以基于与预先表征的难以制造的图案的匹配来确定所绘制的半导体设计布局内的难以制造的图案，基于预定的相关性来确定校正的图案 在校正图案和预先表征的难以制造图案之间，并且在所绘制的半导体设计布局内用修正图案代替难以制造的图案。

公开(公告)号：US20130212548A1

公开(公告)日：2013-08-15

申请号：US13369938

申请日：2012-02-09

申请人： Swamy Muddu ,  Abde Ali Kagalwalla ,  Luigi Capodieci

发明人： Swamy Muddu ,  Abde Ali Kagalwalla ,  Luigi Capodieci

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule.

摘要翻译： 提供了方法和设备，用于分析设计规则对布局的影响。 一个示例性方法涉及为规则的不同值生成布局的变体，确定每个布局变体的设备度量的值，以及基于对应于设备度量的设备度量的值来识别规则与设备度量之间的关系 规则的不同值。 在一个实施例中，通过使用规则的不同值来根据规则的初始值生成的初始布局来执行布局压缩来生成布局变体。

公开(公告)号：US20100099032A1

公开(公告)日：2010-04-22

申请号：US12254172

申请日：2008-10-20

申请人： Yi Zou ,  Luigi Capodieci

发明人： Yi Zou ,  Luigi Capodieci

IPC分类号： G03F1/00

CPC分类号： G03F1/36

摘要： An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns, and inverse lithography is performed on the unique feature layouts to form assist features. The resulting layout of assist features is analyzed to create an assist feature rules set. The rules can then be applied to a photomask patterned with the integrated circuit design layout to print optimal assist features. The resulting photomask may be used to form an integrated circuit on a semiconductor substrate.

摘要翻译： 使用反光刻法创建集成电路设计布局的最佳辅助特征规则集。 全芯片布局被光刻仿真，并确定了可印刷性故障区域。 对特征布局图案进行特征分析，并对独特特征布局进行反光刻以形成辅助特征。 分析所得到的辅助特征布局以创建辅助特征规则集。 然后可以将规则应用于利用集成电路设计布局图案化的光掩模，以打印最佳辅助特征。 所得到的光掩模可用于在半导体衬底上形成集成电路。

公开(公告)号：US20050229125A1

公开(公告)日：2005-10-13

申请号：US10816764

申请日：2004-04-02

申请人： Cyrus Tabery ,  Todd Lukanc ,  Chris Haidinyak ,  Luigi Capodieci ,  Carl Babcock ,  Hung-eil Kim ,  Christopher Spence

发明人： Cyrus Tabery ,  Todd Lukanc ,  Chris Haidinyak ,  Luigi Capodieci ,  Carl Babcock ,  Hung-eil Kim ,  Christopher Spence

IPC分类号： G03F7/20 ,  G06F17/50

CPC分类号： G03F7/70433 ,  G03F7/705

摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

摘要翻译： 选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。 对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。 可以选择提供最佳可制造性的RET。 以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

公开(公告)号：US6040118A

公开(公告)日：2000-03-21

申请号：US183356

申请日：1998-10-30

申请人： Luigi Capodieci

发明人： Luigi Capodieci

IPC分类号： G03F7/20

CPC分类号： G03F7/203 ,  G03F7/2022

摘要： A method (100) of providing critical dimension uniformity in a radiation sensitive film (104) includes the steps of forming (102) the radiation sensitive film (104) over a substrate (106) and exposing (110) the radiation sensitive film (104) to radiation (56) using a mask (50) having a pattern thereon, wherein a first feature (52) and a second feature (54) on the mask (50) are intended to provide the same critical dimension on the radiation sensitive film (104). The exposure step (110) creates a non-uniform exposure pattern (60) on the radiation sensitive film (104) corresponding to the mask pattern due to various anomalies in the exposure process or in the mask itself. A transferred first feature (84) critical dimension on the radiation sensitive film (104) which corresponds to the first mask feature (52) is larger than the second transferred feature (86) critical dimension which corresponds to the second mask feature (54) due to the radiation non-uniformities or imaging non-uniformities. The method (100) further includes exposing (140) the radiation sensitive film (104) to a blanket radiation exposure (150), wherein the blanket radiation exposure (150) provides effectively a greater dose to the first transferred feature (84) than the radiation dose to the second transferred feature (86) due to variations in a bleaching of the radiation sensitive film (104) at edges (130, 132) of the first and second transferred features (84, 86) due to the first exposure (110). Therefore the blanket exposure step (140) decreases the critical dimension of the first transferred feature (84) more than the critical dimension size of the second transferred feature (86), thereby reducing a difference in the critical dimension of the first and second transferred features (84, 86) which results in improved critical dimension uniformity.

公开(公告)号：US08589844B2

公开(公告)日：2013-11-19

申请号：US13369938

申请日：2012-02-09

申请人： Swamy Muddu ,  Abde Ali Kagalwalla ,  Luigi Capodieci

发明人： Swamy Muddu ,  Abde Ali Kagalwalla ,  Luigi Capodieci

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081

摘要： Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule.

摘要翻译： 提供了方法和设备，用于分析设计规则对布局的影响。 一个示例性方法涉及为规则的不同值生成布局的变体，确定每个布局变体的设备度量的值，以及基于对应于设备度量的设备度量的值来识别规则与设备度量之间的关系 规则的不同值。 在一个实施例中，通过使用规则的不同值来根据规则的初始值生成的初始布局来执行布局压缩来生成布局变体。

公开(公告)号：US20130219347A1

公开(公告)日：2013-08-22

申请号：US13400445

申请日：2012-02-20

申请人： Yi Zou ,  Swamy Muddu ,  Lynn T. Wang ,  Vito Dai ,  Luigi Capodieci ,  Peng Xie

发明人： Yi Zou ,  Swamy Muddu ,  Lynn T. Wang ,  Vito Dai ,  Luigi Capodieci ,  Peng Xie

IPC分类号： G06F17/50

CPC分类号： G03F1/70

摘要： Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.

摘要翻译： 提供制造半导体器件的方法。 在一个实施例中，制造半导体器件的方法包括扫描电路设计布局并提出用于分解布局的图案。 然后将所提出的模式与包括禁止模式类别和优选模式类别的先前模式的库进行比较。 如果所选择的提议模式匹配禁止模式，则删除所选择的提议模式。 如果所选择的提出的模式匹配优选模式，则所选择的提出的模式被识别用于分解的布局。 分辨的布局是从识别的图案生成的。 基于分解的布局制造多个掩模。 然后用半导体衬底上的多个掩模进行多重图形化光刻技术。

公开(公告)号：US20130198696A1

公开(公告)日：2013-08-01

申请号：US13361595

申请日：2012-01-30

申请人： Lynn T. Wang ,  Sriram Madhavan ,  Luigi Capodieci

发明人： Lynn T. Wang ,  Sriram Madhavan ,  Luigi Capodieci

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/70

摘要： A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.

摘要翻译： 公开了一种用于制造集成电路的方法，其包括根据实施例，为集成电路提供双重图案化技术兼容的逻辑设计，所述逻辑设计包括多个元件; 对所述多个元素中的一个或多个元素的设计进行评分以产生设计得分; 至少部分基于设计得分修改设计; 生成实现修改后的逻辑设计的掩码集; 并采用掩模组来实现半导体衬底中的逻辑设计。