公开(公告)号：US11515471B2

公开(公告)日：2022-11-29

申请号：US16988707

申请日：2020-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Jung Chiu ,  Ya-Sheng Feng ,  I-Ming Tseng ,  Yi-An Shih ,  Yu-Chun Chen ,  Yi-Hui Lee ,  Chung-Liang Chu ,  Hsiu-Hao Hu

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

公开(公告)号：US11011575B2

公开(公告)日：2021-05-18

申请号：US16655251

申请日：2019-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Sheng Feng ,  Yu-Chun Chen ,  Chiu-Jung Chiu

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/10 ,  H01F10/32 ,  H01L43/02

Abstract: A circuit selector of embedded magnetoresistive random access memory (EMRAM) includes a transistor comprising a source/drain terminal coupled to a first magnetic tunneling junction (MTJ) and a second MTJ, a gate terminal, and a drain/source terminal coupled to a voltage source. Preferably, the first MTJ includes a first free layer, a first barrier layer, and a first pinned layer, in which the first free layer is coupled to the source/drain terminal and the first pinned layer is coupled to a first circuit. The second MTJ includes a second free layer, a second barrier layer, and a second pinned layer, in which the second pinned layer is coupled to the source/drain terminal and the second free layer is coupled to a second circuit.

公开(公告)号：US20210083002A1

公开(公告)日：2021-03-18

申请号：US16655251

申请日：2019-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Sheng Feng ,  Yu-Chun Chen ,  Chiu-Jung Chiu

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01L43/10

Abstract: A circuit selector of embedded magnetoresistive random access memory (EMRAM) includes a transistor comprising a source/drain terminal coupled to a first magnetic tunneling junction (MTJ) and a second MTJ, a gate terminal, and a drain/source terminal coupled to a voltage source. Preferably, the first MTJ includes a first free layer, a first barrier layer, and a first pinned layer, in which the first free layer is coupled to the source/drain terminal and the first pinned layer is coupled to a first circuit. The second MTJ includes a second free layer, a second barrier layer, and a second pinned layer, in which the second pinned layer is coupled to the source/drain terminal and the second free layer is coupled to a second circuit.

公开(公告)号：US10665772B2

公开(公告)日：2020-05-26

申请号：US16178542

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ya-Sheng Feng ,  Chiu-Jung Chiu ,  Hung-Chan Lin

IPC: H01L43/02 ,  H01F10/32 ,  H01L23/535 ,  H01L43/12 ,  H01F41/34 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, wherein the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.

公开(公告)号：US20200111950A1

公开(公告)日：2020-04-09

申请号：US16178542

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ya-Sheng Feng ,  Chiu-Jung Chiu ,  Hung-Chan Lin

IPC: H01L43/02 ,  H01F10/32 ,  H01L23/535 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, wherein the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.

公开(公告)号：US10249528B2

公开(公告)日：2019-04-02

申请号：US15681419

申请日：2017-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Jung Chiu ,  Hung-Chan Lin ,  Yu-Chun Chen

IPC: H01L21/762 ,  H01L21/02 ,  H01L27/06 ,  H01L21/768 ,  H01L29/94 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/28

Abstract: An integrated circuit includes a first insulation layer, a bottom plate, a first patterned dielectric layer, a medium plate, a second patterned dielectric layer, and a top plate. The first patterned dielectric layer is disposed on the bottom plate. The medium plate is disposed on the first patterned dielectric layer. At least a part of the first patterned dielectric layer and the medium plate and a part of the bottom plate are disposed in a first trench penetrating the first insulation layer. The bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor. The second patterned dielectric layer is disposed on the medium plate. The top plate is disposed on the second patterned dielectric layer. The medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor. The bottom plate is electrically connected with the top plate.