公开(公告)号：US20240090342A1

公开(公告)日：2024-03-14

申请号：US18511984

申请日：2023-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H10N50/80 ,  H01L21/768 ,  H10N50/01

CPC classification number: H10N50/80 ,  H01L21/76801 ,  H01L21/76838 ,  H10N50/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

公开(公告)号：US11476410B2

公开(公告)日：2022-10-18

申请号：US16997922

申请日：2020-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Yen-Chun Liu ,  Ya-Sheng Feng ,  Chiu-Jung Chiu ,  I-Ming Tseng ,  Yi-An Shih ,  Yi-Hui Lee ,  Chung-Liang Chu ,  Hsiu-Hao Hu

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10

Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.

公开(公告)号：US20220013713A1

公开(公告)日：2022-01-13

申请号：US16988707

申请日：2020-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Jung Chiu ,  Ya-Sheng Feng ,  I-Ming Tseng ,  Yi-An Shih ,  Yu-Chun Chen ,  Yi-Hui Lee ,  Chung-Liang Chu ,  Hsiu-Hao Hu

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

公开(公告)号：US10797226B2

公开(公告)日：2020-10-06

申请号：US16148852

申请日：2018-10-01

Applicant: United Microelectronics Corp.

Inventor： Ya-Sheng Feng ,  Yu-Chun Chen ,  Chiu-Jung Chiu ,  Hung-Chan Lin

IPC: H01L43/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01F10/32 ,  H01L27/22 ,  H01F41/34 ,  G11C11/16 ,  H01L43/12

Abstract: A magnetoresistive memory cell is provided including a substrate. An inter-layer dielectric layer is disposed on the substrate. A via structure is disposed in the inter-layer dielectric layer. A magnetic pinned layer is disposed on the via structure. A tunnel barrier layer is disposed on the magnetic pinned layer to cover a top and a sidewall of the magnetic pinned layer, wherein the tunnel barrier layer comprises a horizontal extending portion outward from a bottom of the sidewall. A magnetic free layer with a -like structure is disposed on the tunnel barrier layer, wherein the magnetic free layer is isolated from the magnetic pinned layer by the tunnel bather layer. A spacer is disposed on the sidewall of the magnetic free layer. The spacer extends to the inter-layer dielectric layer.

公开(公告)号：US20240090341A1

公开(公告)日：2024-03-14

申请号：US18511974

申请日：2023-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H10N50/80 ,  H01L21/768 ,  H10N50/01

CPC classification number: H10N50/80 ,  H01L21/76801 ,  H01L21/76838 ,  H10N50/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

公开(公告)号：US20220416154A1

公开(公告)日：2022-12-29

申请号：US17902895

申请日：2022-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H01L43/02 ,  H01L21/768 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

公开(公告)号：US11469368B2

公开(公告)日：2022-10-11

申请号：US16207206

申请日：2018-12-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H01L43/02 ,  H01L21/768 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

公开(公告)号：US20200013949A1

公开(公告)日：2020-01-09

申请号：US16056551

申请日：2018-08-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Sheng Feng ,  Hung-Chan Lin ,  Yu-Ping Wang ,  Yu-Chun Chen ,  Chiu-Jung Chiu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.

公开(公告)号：US11239412B2

公开(公告)日：2022-02-01

申请号：US16686272

申请日：2019-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ya-Sheng Feng ,  Chiu-Jung Chiu

IPC: H01L43/02 ,  H01L43/12

Abstract: A semiconductor structure includes an electrode element with an upper surface. The upper surface includes at least one convex curved portion.

公开(公告)号：US11087812B1

公开(公告)日：2021-08-10

申请号：US16931438

申请日：2020-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Hui Lee ,  I-Ming Tseng ,  Chiu-Jung Chiu ,  Chung-Liang Chu ,  Yu-Chun Chen ,  Ya-Sheng Feng ,  Yi-An Shih ,  Hsiu-Hao Hu ,  Yu-Ping Wang

IPC: G11C16/08 ,  G11C11/16

Abstract: A MRAM includes a plurality of memory cells, an operation unit, a voltage generator, and an input/output circuit. The operation unit includes multiple groups of memory cells among the plurality of memory cells. The voltage generator is configured to provide a plurality of control signals by voltage-dividing a voltage control signal and selectively output the plurality of control signals to the input/output circuit. The input/output circuit is configured to output a plurality of switching pulse signals to the multiple groups of memory cells according to the plurality of control signals, wherein each switching pulse signal differs in pulse width or level.