公开(公告)号：US20250098557A1

公开(公告)日：2025-03-20

申请号：US18380212

申请日：2023-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Jiun Chang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

Abstract: A resistive random access memory device includes a substrate; a dielectric layer disposed on the substrate; a conductive via disposed in the dielectric layer; a metal nitride layer disposed on the conductive via, wherein the metal nitride has a gradient nitrogen concentration along a thickness direction of the metal nitride layer; a resistive switching layer disposed on the metal nitride layer; and a metal oxynitride layer disposed on the resistive switching layer, wherein the metal oxynitride layer has a gradient nitrogen concentration along a thickness direction of the metal oxynitride layer.

公开(公告)号：US20250048944A1

公开(公告)日：2025-02-06

申请号：US18237915

申请日：2023-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Jiun Chang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

Abstract: A resistive switching device includes a substrate, a first dielectric layer on the substrate, a conductive via in the first dielectric layer, and a resistive switching structure embedded in an upper portion of the conductive via. The resistive switching structure includes a top electrode layer having a lower sharp corner, a resistive switching material layer disposed around the lower sharp corner of the top electrode layer, and a bottom electrode layer disposed between the resistive switching material layer and the upper portion of the conductive via.

公开(公告)号：US20240057487A1

公开(公告)日：2024-02-15

申请号：US17938926

申请日：2022-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Jiun Chang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/1233 ,  H01L45/146 ,  H01L45/1675 ,  H01L27/2472 ,  G11C13/0007

Abstract: An RRAM includes a bottom electrode, a resistive switching layer and a top electrode. The bottom electrode includes an inverted T-shaped profile. The resistive switching layer covers the bottom electrode. The top electrode covers the resistive switching layer. The inverted T-shaped profile includes a bottom element and a vertical element. The vertical element is disposed on the bottom element. The shape of the vertical element includes a rectangle or a trapezoid.

公开(公告)号：US20200350317A1

公开(公告)日：2020-11-05

申请号：US16931397

申请日：2020-07-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Chung-Yen Feng

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

公开(公告)号：US10756090B2

公开(公告)日：2020-08-25

申请号：US15922899

申请日：2018-03-15

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Chung-Yen Feng

IPC: H01L21/8242 ,  H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L21/02

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

公开(公告)号：US10312242B2

公开(公告)日：2019-06-04

申请号：US15986780

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chieh Chen ,  Pin-Hong Chen ,  Chih-Chieh Tsai ,  Chia-Chen Wu ,  Yi-An Huang ,  Kai-Jiun Chang ,  Tsun-Min Cheng ,  Yi-Wei Chen

IPC: H01L23/31 ,  H01L27/108

Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.

公开(公告)号：US10276389B1

公开(公告)日：2019-04-30

申请号：US15987887

申请日：2018-05-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Yi-Wei Chen ,  Pin-Hong Chen ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chun-Chieh Chiu ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L27/108

Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a first metal silicon nitride layer on the silicon layer; performing an oxygen treatment process to form an oxide layer on the first metal silicon nitride layer; forming a second metal silicon nitride layer on the oxide layer; forming a conductive layer on the second metal silicon nitride layer; and patterning the conductive layer, the second metal silicon nitride layer, the oxide layer, the first metal silicon nitride layer, and the silicon layer to form a gate structure.

公开(公告)号：US09773789B1

公开(公告)日：2017-09-26

申请号：US15260292

申请日：2016-09-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Kai-Jiun Chang

IPC: H01L29/49 ,  H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10897

Abstract: A dynamic random access memory (DRAM) device includes a substrate, plural buried gates and plural bit lines. The buried gates are disposed in the substrate along a first trench extending along a first direction. The bit lines are disposed over the buried gates and extending along a second direction across the first direction. Each of the bit lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes WSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof.

公开(公告)号：US11251187B2

公开(公告)日：2022-02-15

申请号：US15712151

申请日：2017-09-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Chia-Chen Wu ,  Kai-Jiun Chang ,  Yi-An Huang ,  Tsun-Min Cheng

IPC: H01L27/108

Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

公开(公告)号：US10804365B2

公开(公告)日：2020-10-13

申请号：US15985730

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chun-Chieh Chiu ,  Pin-Hong Chen ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chia-Chen Wu ,  Tzu-Hao Liu

IPC: H01L21/02 ,  H01L29/49 ,  H01L27/108 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L21/285

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.