公开(公告)号：US12075613B2

公开(公告)日：2024-08-27

申请号：US17570345

申请日：2022-01-06

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Chia-Chen Wu ,  Kai-Jiun Chang ,  Yi-An Huang ,  Tsun-Min Cheng

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/34

Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

公开(公告)号：US11222784B2

公开(公告)日：2022-01-11

申请号：US16831827

申请日：2020-03-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Hao Liu ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Po-Chih Wu ,  Pin-Hong Chen ,  Chun-Chieh Chiu ,  Tzu-Chieh Chen ,  Chih-Chien Liu ,  Chih-Chieh Tsai ,  Ji-Min Lin

IPC: H01L21/28 ,  G11C11/4097 ,  H01L27/108

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.

公开(公告)号：US20200227264A1

公开(公告)日：2020-07-16

申请号：US16831827

申请日：2020-03-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Hao Liu ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Po-Chih Wu ,  Pin-Hong Chen ,  Chun-Chieh Chiu ,  Tzu-Chieh Chen ,  Chih-Chien Liu ,  Chih-Chieh Tsai ,  Ji-Min Lin

IPC: H01L21/28 ,  G11C11/4097 ,  H01L27/108

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.

公开(公告)号：US10374051B1

公开(公告)日：2019-08-06

申请号：US15987891

申请日：2018-05-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ji-Min Lin ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Pin-Hong Chen ,  Chih-Chien Liu ,  Chun-Chieh Chiu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Yi-An Huang ,  Kai-Jiun Chang

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/43

Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a metal silicon nitride layer on the silicon layer; forming a stress layer on the metal silicon nitride layer; performing a thermal treatment process; removing the stress layer; forming a conductive layer on the metal silicon nitride layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

公开(公告)号：US20190067296A1

公开(公告)日：2019-02-28

申请号：US15712151

申请日：2017-09-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Chia-Chen Wu ,  Kai-Jiun Chang ,  Yi-An Huang ,  Tsun-Min Cheng

IPC: H01L27/108

Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

公开(公告)号：US09953982B1

公开(公告)日：2018-04-24

申请号：US15468084

申请日：2017-03-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L21/28 ,  H01L29/423 ,  H01L21/033

CPC classification number: H01L27/10823 ,  H01L21/28008 ,  H01L21/76224 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/4236

Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in a substrate; removing part of the STI to form a first trench; forming a cap layer in the first trench; forming a mask layer on the cap layer and the substrate; and removing part of the mask layer, part of the cap layer, and part of the STI to form a second trench.

公开(公告)号：US20250008745A1

公开(公告)日：2025-01-02

申请号：US18221872

申请日：2023-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Jiun Chang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20 ,  H10N79/00

Abstract: An RRAM structure includes a bottom electrode, a resistive switching layer, a top electrode, a spacer and a conductive line. The bottom electrode is a first cylinder. The resistive switching layer includes a second cylinder and a three-dimensional disk. A first bottom of the second cylinder directly contacts a top surface of the three-dimensional disk. The top electrode is a third cylinder. The third cylinder includes a top base, a second bottom base and a sidewall. The first cylinder is embedded within the second cylinder and the three-dimensional disk. The second cylinder is embedded within the third cylinder and the second bottom base of the third cylinder directly contacts the top surface of the three-dimensional disk. The spacer surrounds and directly contacts a side surface of the three-dimensional disk. The conductive line encapsulates the top base and the sidewall of the third cylinder.

公开(公告)号：US11877433B2

公开(公告)日：2024-01-16

申请号：US16931397

申请日：2020-07-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Chung-Yen Feng

IPC: H01L23/48 ,  H10B12/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L21/02

CPC classification number: H10B12/0335 ,  H01L21/28568 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76831 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53266 ,  H01L28/91 ,  H10B12/31 ,  H10B12/315 ,  H01L21/0217 ,  H01L21/0228

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

公开(公告)号：US10651040B2

公开(公告)日：2020-05-12

申请号：US15986797

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Hao Liu ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Po-Chih Wu ,  Pin-Hong Chen ,  Chun-Chieh Chiu ,  Tzu-Chieh Chen ,  Chih-Chien Liu ,  Chih-Chieh Tsai ,  Ji-Min Lin

IPC: H01L21/28 ,  G11C11/4097 ,  H01L27/108

Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

公开(公告)号：US10211211B1

公开(公告)日：2019-02-19

申请号：US15830006

申请日：2017-12-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Kai-Jiun Chang ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chia-Chen Wu ,  Pin-Hong Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Yi-An Huang

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/778 ,  H01L29/45 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/4763 ,  H01L27/108 ,  H01L23/532 ,  H01L21/02 ,  H01L23/535

Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a barrier layer in the trench; performing a soaking process to reduce chlorine concentration in the barrier layer; and forming a conductive layer to fill the trench.